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| ST52F501L/F502L (R) ST52F501L/F502L TARGET SPECIFICATION 8-BIT INTELLIGENT CONTROLLER UNIT (ICU) IR Driver, Timer/PWM, I2C, SPI, SCI, Low Voltage Memories s Up to 8 Kbytes Single Voltage Flash Memory s s s s s 256 bytes of Register File 256 bytes of RAM 256 bytes Data EEPROM (F502L only) In Situ Programming in Flash devices (ISP) Single byte and Page modes and In Application Programming for writing data in Flash memory Readout protection and flexible write protection s Core s Register File based architecture s s s 107 basic instructions Hardware multiplication and division Decision Processor for the implementation of Fuzzy Logic algorithms Deep System and User Stacks s s Interrupts 10 interrupt vectors with one SW Trap Non-Maskable Interrupt (NMI) Two Port Interrupts with up to 24 sources s s Clock and Power Supply Up to 24 MHz clock frequency Programmable Oscillator modes: - Internal Oscillator with four programmable frequencies (1.25, 2.5, 5, 10 MHz 1%) - External Clock/ Oscillator - External RC Oscillator s s Peripherals s Programmable 8-bit Timer/PWM with internal 16-bit Prescaler featuring PWM or Pulse output, Input capture and Output compare. s s s s s s s Low Voltage supply (1.8 - 3.6 V) Power Down Reset (PDR) protection Power-On Reset (POR) Programmable Low Voltage Detector (PLVD) Power Saving features Programmable Halt mode Wakeup (PHW) with internal 32 KHz oscillator Low consumption in Halt Mode with PHW and PDR enabled. Programmable 8-bit Timer/PWM with internal 16-bit Prescaler and IR Driver for remote control Watchdog timer I2CTM Peripheral with master and slave mode 3-wire SPITM Peripheral supporting Single Master and Multi Master SPI modes Serial Communication Interface (SCI) with asynchronous protocol (UART) s s s s s s I/O Ports From 14 up to 24 I/O PINs configurable in pullup, push-pull, weak pull-up, open-drain and high-impedance High current sink/source in all pins Development tools s High level Software tools s s s s `C' Compiler Emulator Low cost Programmer Gang Programmer s Rev 1.3 - June 2003 1/106 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice. ST52F501L/F502L 2/106 ST52F501L/F502L TABLE OF CONTENTS TABLE OF CONTENTS 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.2.1 Memory Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2.2 Working Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2 ADDRESSING SPACES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.2 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.3 Program/Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.4 System and User Stacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.5 Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.6 Output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.7 Configuration Registers & Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3 INTERNAL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 Control Unit and Data Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.1.1 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.2 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4 MEMORY PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 Program/Data Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 4.2 Memory Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.2.1 Programming Mode start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2.2 Fast Programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2.3 Random data writing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2.4 Option Bytes Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3 Memory Verify. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.3.1 Fast read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3.2 Random data reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.4 Memory Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.5 ID Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.6 Error cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.7 In-Situ Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4.8 In-Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4.8.1 Single byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.8.2 Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.8.3 Memory Corruption Prevention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.8.4 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.8.5 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3/106 ST52F501L/F502L 5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 5.2 Global Interrupt Request Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 5.3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 5.4 Interrupt Maskability and Priority Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 5.5 Interrupt RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 6 CLOCK, RESET & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 6.2 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 6.2.1 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.2.2 Power Down Reset (PDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.2.3 POR & Reset Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3 Programmable Low Voltage Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 6.4 Power Saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 6.4.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.4.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.5 Programmable Halt mode Wake-up (PHW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 6.6.1 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.6.2 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.6.3 Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7 FUZZY COMPUTATION (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.1 Fuzzy Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 7.2 Fuzzyfication Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 7.3 Inference Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 7.4 Defuzzyfication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 7.5 Input Membership Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 7.6 Output Singleton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 7.7 Fuzzy Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 8.2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 8.3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 8.4 Interrupt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 8.5 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 8.6.1 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.6.2 Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.6.3 Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4/106 ST52F501L/F502L 9 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 9.2 Instruction Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 10 WATCHDOG TIMER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 10.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 11 PWM/TIMERS and IR Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 11.2 Timer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 11.3 PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 11.3.1 Simultaneous Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.4 Timer Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 11.5 PWM/Timer output modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 11.5.1 Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.5.2 IR Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.6 PWM/Timer 0 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 11.6.1 PWM/Timer 0 Input Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.6.2 PWM/Timer 0 Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.7 PWM/Timer 1 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 11.7.1 PWM/Timer 1 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.7.2 PWM/Timer 1 Input Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.7.3 PWM/Timer 1 Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12 SERIAL COMMUNICATION INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.1 SCI Receiver block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 12.1.1 Recovery Buffer Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.1.2 SCDR_RX Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.2 SCI Transmitter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 12.3 Baud Rate Generator Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 12.4 SCI Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 12.4.1 SCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12.4.2 SCI Input Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.4.3 SCI Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 13.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 13.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 13.3.1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 13.3.2 Communication Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 13.3.3 SDA/SCL Line Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 13.4.1 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5/106 ST52F501L/F502L 13.4.2 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 13.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 13.5.1 I2C Interface Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.5.2 I2C Interface Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 13.5.3 I2C Interface Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 14.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 14.3 General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 14.4.1 Master Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.4.2 Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.4.3 Data Transfer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.4.4 Write Collision Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.4.5 Master Mode Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 14.4.6 Overrun Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 14.4.7 Single Master and Multimaster Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 14.4.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 14.5 SPI Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 14.5.1 SPI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 14.5.2 SPI Input Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.5.3 SPI Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6/106 ST52F501L/F502L 1 GENERAL DESCRIPTION 1.1 Introduction ST52F501L/F502L are devices of ST FIVE family of 8-bit Intelligent Controller Units (ICU), which can perform, both boolean and Fuzzy algorithms in an efficient manner, in order to reach the best performances that the two methodologies allow. Produced by STMicroelectronics using the reliable high performance low power/low voltage CMOS process for Single Voltage Flash versions, ST52F501L/F502L include integrated on-chip peripherals that allow maximization of system reliability, and decreased system costs in order to minimize the number of external components, in particular it is suitable for portable applications. The flexible I/O configuration of ST52F501L/F502L allow one to interface with a wide range of external devices (for example D/A converters or power control devices), and to communicate with the most common serial standards. ST52F501L/F502L pins are configurable. The user can set input or output signals on each single pin in 8 different modes, reducing the need for external components in order to supply a suitable interface with the port pins. A hardware multiplier and divider, together with a wide instruction set, allow the implementation of complex functions by using a single instruction. Therefore, program memory utilization and computational speed is optimized. Fuzzy Logic dedicated structures in ST52F501L/ F502L ICU's can be exploited to model complex system with high accuracy in a useful and simple manner. Fuzzy Expert Systems for overall system management and Fuzzy Real time Controls can be designed to increase performance at competitive costs. The linguistic approach characterizing Fuzzy Logic is based on a set of IF-THEN rules, which describe the control behavior and on Membership Functions associated with input and output variables. Up to 340 Membership Functions, with triangular and trapezoidal shapes, or singleton values are available to describe fuzzy variables. The Timer/PWM peripheral allows one to manage power devices and timing signals, by implementing different operating modes and high frequency PWM (Pulse Width Modulation) controls. Input Capture and Output Compare functions are available on the Timers. The Timer has a 16-bit programmable internal Prescaler and a 8-bit Counter, which can use internal or external START/STOP signals and clock. In addition to the features described previously, a second PWM/Timer includes an IR Driver that can directly support a wide set of codification types for remote control signals. The outputs of the two Timers/PWM can also be easily combined in AND, OR, XOR and NOT to generate complex digital waveforms. An internal programmable WATCHDOG is available to avoid loop errors and reset the ICU. ST52F501L/F502L supply different peripherals to implement the most common serial communication protocols. I2C, SPI and SCI peripherals allow the implementation of synchronous and asynchronous serial protocols. I2C peripherals can work both in master and slave mode. SPI implements Single and Multi Master modes using 3-wire. SCI implements the standard UART protocols. Up to 10 interrupt vectors are available, which allow synchronization with peripherals and external devices. Non-Maskable Interrupt and S/W TRAP are available. All interrupts have configurable priority levels and are maskable excluding the Non-Maskable Interrupt, which has fixed top level priority. Two versatile Port Interrupts are available for synchronization with external sources. The ST52F501L/F502L also include an on-chip Power-on-Reset (POR), which provides an internal chip reset during power up situation and a Programmable Low Voltage Detector (PLVD), which causes the ICU to send an interrupt request or a reset if the voltage source VDD dips below a threshold. Three programmable thresholds are available to work with different supply voltages. The Power Down Reset (PDR) provides a reset of the device if the voltage source VDD dips below the safe supply voltage level (around 1.8 V) even in Halt mode. In order to optimize energy consumption, two different power saving modes are available: Wait mode and Halt mode. The Programmable Halt mode Wake-up (PHW) allows the CPU to wake-up from Halt mode at user programmed times, either servicing a dedicated interrupt routine or resetting the device. The PHW is driven by a dedicated 32 KHz low consumption internal oscillator. Internal Oscillator with programmable frequency (1.25 to 10 MHz 1%) is available. External clock, quartz oscillator or RC oscillator are also applicable. The device always starts with the Internal Oscillator, then it reads an Option Byte where the clock mode to be used is programmed. Program Memory addressing capability addresses up to 8 Kbytes of memory location to store both program instructions and data. 7/106 ST52F501L/F502L Memory can be locked by the user in order to prevent external undesired operations. Operations may be performed on data stored in RAM, allowing direct combination of new inputs and feedback data. All RAM bytes are used like Register File. An additional RAM bench is added to the Program Memory addressing space in order to allow the management of the System/User Stacks and user data storage. ST52F501L/F502L supply the system stack and the user stack located in the additional RAM bench. The user stack can be located anywhere in the additional RAM by writing the top address in the configuration registers, in order to avoid overlap with other data. Single Voltage Flash allows the user to reprogram the devices on-board by means of the In Situ Programming (ISP) feature. It is possible to store in safe way up to 256 bytes of data in the available EEPROM memory benches (ST52F502L only). Permanent data, both in Flash and EEPROM can be managed by means of the In-ApplicationProgramming (IAP) feature. Single byte and Page write modes are supported. Flexible write protection, of permanent data or program instructions, is also available. The Instruction Set composed of up to 107 instructions allows code compression and high speed in the program implementation. A powerful development environment consisting of a board and software tools allows an easy configuration and use of ST52F501L/F502L. The V is u al FI VE s o ftw ar e to ol a ll o ws th e development and debugging of projects via a userfriendly graphical interface and optimization of generated microcode. Third-party Hardware Emulators and `C' Compiler ar e av ai la bl e to s pe ed- u p the app li ca tio n implementation and time-to-market. 1.2.1 Memory Programming Mode. The ST52F501L/F502L memory is loaded in the Memory Programming Mode. All instructions and data are written inside the memory during this phase. The Option Bytes are loaded during this phase by using the programming tools. The Option Bytes can only be loaded in this phase and cannot be modified run-time. Data and commands are transmitted by using the I2C protocol, implemented using the internal I2C peripheral. The In-Situ Programming protocol (ISP) uses the following pins: s SDA and SCL for transmission s s s Vpp for entering in the mode RESET for starting the protocol in a stable status Vdd and Vss for the power supply. The Internal clock is used in this phase. 1.2.2 Working Mode. The processor starts the working phase following the instructions, which have been previously loaded in the first locations of the memory. The first instruction must be a jump to the first program instruction, skipping the data (interrupt vectors, Membership Functions, user data) stored in the first memory page. ST52F501L/F502L's internal structure includes two computational blocks, the CONTROL UNIT (CU) and the DATA PROCESSING UNIT (DPU), which performs boolean functions. The DECISION PROCESSOR (DP) block cooperates with these blocks to perform Fuzzy algorithms. The DP can manage up to 340 different Membership Functions for the antecedent part of fuzzy rules. The consequent terms of the rules are "crisp" values (real numbers). The maximum number of rules that can be defined is limited by the dimensions of the standard algorithm implemented. The Program/Data Memory is shared between Fuzzy and standard algorithms. Within this memory, the user data can be stored both in non volatile memory as well as in the RAM locations. The Control Unit (CU) reads information and the status of the peripherals. Arithmetic calculus can be performed on these values by using the internal CU and Register File, which supports all computations. The peripheral inputs can be Fuzzy and/or arithmetic output values contained in the Register File or Program/ Data Memory. 1.2 Functional Description ST52F501L/F502L ICU's can work in two modes according to the Vpp signal levels: s Memory Programming Mode s Working Mode During Working Mode Vpp must be tied to Vss. To enter the Memory Programming Mode, the Vpp pin must be tied to Vdd. A RESET signal must be applied to the device to switch from one mode to the other. 8/106 ST52F501L/F502L Table 1.1 ST52F501L/F502L Device Summary Device ST52F501LF1B6 ST52F501LF1M6 ST52F501LG1M6 ST52F501LG1B6 ST52F501LK1T6 ST52F501LF2B6 ST52F501LF2M6 ST52F501LG2M6 ST52F501LG2B6 ST52F501LK2T6 ST52F501LF3B6 ST52F501LF3M6 ST52F501LG3M6 ST52F501LG3B6 ST52F501LK3T6 ST52F502LF1B6 ST52F502LF1M6 ST52F502LG1M6 ST52F502LG1B6 ST52F502LK1T6 ST52F502LF2B6 ST52F502LF2M6 ST52F502LG2M6 ST52F502LG2B6 ST52F502LK2T6 ST52F502LF3B6 ST52F502LF3M6 ST52F502LG3M6 ST52F502LG3B6 ST52F502LK3T6 NVM 2K FLASH 2K FLASH 2K FLASH 2K FLASH 2K FLASH 4K FLASH 4K FLASH 4K FLASH 4K FLASH 4K FLASH 8K FLASH 8K FLASH 8K FLASH 8K FLASH 8K FLASH 2K FLASH 2K FLASH 2K FLASH 2K FLASH 2K FLASH 4K FLASH 4K FLASH 4K FLASH 4K FLASH 4K FLASH 8K FLASH 8K FLASH 8K FLASH 8K FLASH 8K FLASH RF 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 RAM 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 EEPROM 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 Timers 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit 2X8-bit IR-DRV Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PHW Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Comms I2C-SCI-SPI I2C-SCI-SPI I2C-SCI-SPI I C-SCI-SPI I C-SCI-SPI I C-SCI-SPI I C-SCI-SPI I2C-SCI-SPI I2C-SCI-SPI I2C-SCI-SPI I C-SCI-SPI I2C-SCI-SPI I C-SCI-SPI I2C-SCI-SPI I2C-SCI-SPI I2C-SCI-SPI I C-SCI-SPI I2C-SCI-SPI I C-SCI-SPI I C-SCI-SPI I2C-SCI-SPI I2C-SCI-SPI I2C-SCI-SPI I C-SCI-SPI I C-SCI-SPI I C-SCI-SPI I C-SCI-SPI I2C-SCI-SPI I2C-SCI-SPI I2C-SCI-SPI 2 2 2 2 2 2 2 2 2 2 2 2 2 I/O 14 14 22 24 24 14 14 22 24 24 14 14 22 24 24 14 14 22 24 24 14 14 22 24 24 14 14 22 24 24 Package DIP 20 SO 20 SO 28 SDIP 32 TQFP 32 DIP 20 SO 20 SO 28 SDIP 32 TQFP 32 DIP 20 SO 20 SO 28 SDIP 32 TQFP 32 DIP 20 SO 20 SO 28 SDIP 32 TQFP 32 DIP 20 SO 20 SO 28 SDIP 32 TQFP 32 DIP 20 SO 20 SO 28 SDIP 32 TQFP 32 Table 1.2 ST52F501L/F502L Common Features COMMON FEATURES Watchdog Other Features Temperature Range Operating Supply CPU Frequency ST52F501L/F502L Yes NMI, PLVD, POR, PDR From -40 to + 85 1.8 - 3.6 V up to 24 MHz. 9/106 ST52F501L/F502L Figure 1.1 ST52F501L/F502L Block Diagram I2C MEMORY DATA RAM 256 bytes FLASH ISP/IAP DATA EEPROM MEMORY INTERFACE PORT A PA7:0 TIMER/PWM 0 TIMER/PWM 1 IR DRIVER PORT B CORE ALU & DPU DECISION PROCESSOR CONTROL UNIT Register File 256 bytes Input registers PB7:0 SPI PORT C PC7:0 SCI WATCHDOG PC FLAGS PHW POWER SUPPLY PLVD & PDR OSCILLATORS POWER ON RESET VDD VPP VSS OSCIN OSCOUT RESET 10/106 ST52F501L/F502L Figure 1.2 ST52F501L/F502L SDIP32/SO28 Pin Configuration Vdd VddIO OscOut OscIn Vpp PB0/SCK PB1/MOSI PB2/MISO PB3/SS PB4/TRES PB5/TCLK PB6/T0OUT PB7/T1OUT PC0/SCK PC1/MOSI PC6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 Vss VssIO RESET PA0/SCL PA1/SDA PA2/T1OUT PA3/RX PA4/TSTRT PA5/TCLK/TX PA6/T0OUT PA7/INT PC5/TRES PC4/TX PC3/SS PC2/MISO PC7 Vdd OscOut OscIn Vpp PB0/SCK PB1/MOSI PB2/MISO PB3/SS PB4/TRES PB5/TCLK PB6/T0OUT PB7/T1OUT PC0/SCK PC1/MOSI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 Vss RESET PA0/SCL PA1/SDA PA2/T1OUT PA3/RX PA4/TSTRT PA5/TCLK/TX PA6/T0OUT PA7/INT PC5/TRES PC4/TX PC3/SS PC2/MISO SDIP32 30 29 28 27 26 25 24 23 22 21 20 19 18 17 SO28 26 25 24 23 22 21 20 19 18 17 16 15 Figure 1.3 ST52F501L/F502L SO20/DIP20 Pin Configuration Vdd OscOut OscIn Vpp PB0/SCK PB1/MOSI PB2/MISO PB3/SS PB4/TRES PB5/TCLK 1 2 3 4 5 6 7 8 9 10 20 19 Vss RESET PA0/SCL PA1/SDA PA2/T1OUT PA3/RX PA4/TSTRT PA5/TCLK/TX PA6/T0OUT PA7/INT Vdd OscOut OscIn Vpp PB0/SCK PB1/MOSI PB2/MISO PB3/SS PB4/TRES PB5/TCLK 1 2 3 4 5 6 7 8 9 10 20 19 Vss RESET PA0/SCL PA1/SDA PA2/T1OUT PA3/RX PA4/TSTRT PA5/TCLK/TX PA6/T0OUT PA7/INT SO20 18 17 16 15 14 13 12 11 DIP20 18 17 16 15 14 13 12 11 11/106 ST52F501L/F502L Figure 1.4 ST52F501L/F502L TQFP32 Pin Configuration PA2/T1OUT PA1/SDA 32 Vdd VddIO OscOut OscIn Vpp PB0/SCK PB1/MOSI PB2/MISO 1 2 3 4 5 6 7 8 9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PA5/TCLK/TX PA6/T0OUT PA7/INT PC5/TRES PC4/TX PC3/SS PC2/MISO PC7 10 11 12 13 14 15 16 PB5/TCLK PB3/SS PB6/T0OUT PB4/TRES PC0/SCK 12/106 PB7/T1OUT PC1/MOSI PC6 PA4/TSTRT PA0/SCL PA3/RX VssIO Vss RESET ST52F501L/F502L Table 1.3 ST52F501L/F502L SO28, SO20 & DIP20 Pin List SO28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SO20 DIP20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME Vdd OSCOUT OSCIN Vpp PB0/SCK PB1/MOSI PB2/MISO PB3/SS PB4/TRES PB5/TCLK PB6/T0OUT PB7/T1OUT PC0/SCK PC1/MOSI PC2/MISO PC3/SS PC4/TX PC5/TRES PA7/INT PA6/T0OUT PA5/TCLK/TX PA4/TSTRT PA3/RX PA2/T1OUT PA1/SDA PA0/SCL RESET Vss Serial Data I/O Serial Clock General Reset Digital Ground Programming Mode Selector Programming Phase Digital Power Supply Working Phase Digital Power Supply Oscillator Output Oscillator Input Programming Mode Selector Digital I/O, SPI Serial Clock Digital I/O, SPI Master out Slave in Digital I/O, SPI Master in Slave out Digital I/O, SPI Slave Select Digital I/O, Timer/PWM 0 Reset Digital I/O, Timer/PWM 0 clock Digital I/O, Timer/PWM 0 output Digital I/O, Timer/PWM 1 output Digital I/O, SPI Serial Clock Digital I/O, SPI Master out Slave in Digital I/O, SPI Master in Slave out Digital I/O, SPI Slave Select Digital I/O, SCI Transmission Digital I/O, Timer/PWM 0 Reset Digital I/O, Non Maskable Interrupt Digital I/O, Timer/PWM 0 output Digital I/O, Timer/PWM 0 clock, SCI Transmission Digital I/O, Timer/PWM 0 start/stop Digital I/O, SCI Reception Digital I/O, Timer/PWM 1 output Digital I/O, I2C Serial Data I/O Digital I/O, I2C Serial Clock General Reset Digital Ground 13/106 ST52F501L/F502L Table 1.4 ST52F501L/F502L SDIP32/TQFP32 Pin List SDIP32 TQFP32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME Vdd VddIO OSCOUT OSCIN Vpp PB0/SCK PB1/MOSI PB2/MISO PB3/SS PB4/TRES PB5/TCLK PB6/T0OUT PB7/T1OUT PC0/SCK PC1/MOSI PC6 PC7 PC2/MISO PC3/SS PC4/TX PC5/TRES PA7/INT PA6/T0OUT PA5/TCLK/TX PA4/TSTRT PA3/RX PA2/T1OUT PA1/SDA PA0/SCL RESET VssIO Vss Serial Data I/O Serial Clock General Reset Digital Ground Digital Ground Programming Mode Selector Programming Phase Digital Power Supply Digital Power Supply Working Phase Digital Power Supply Digital I/O Ports Power Supply Oscillator Output Oscillator Input Programming Mode Selector Digital I/O, SPI Serial Clock Digital I/O, SPI Master out Slave in Digital I/O, SPI Master in Slave out Digital I/O, SPI Slave Select Digital I/O, Timer/PWM 0 Reset Digital I/O, Timer/PWM 0 clock Digital I/O, Timer/PWM 0 output Digital I/O, Timer/PWM 1 output Digital I/O, SPI Serial Clock Digital I/O, SPI Master out Slave in Digital I/O Digital I/O Digital I/O, SPI Master in Slave out Digital I/O, SPI Slave Select Digital I/O, SCI Transmission Digital I/O, Timer/PWM 0 Reset Digital I/O, Non Maskable Interrupt Digital I/O, Timer/PWM 0 output Digital I/O, Timer/PWM 0 clock, SCI Transmission Digital I/O, Timer/PWM 0 start/stop Digital I/O, SCI Reception Digital I/O, Timer/PWM 1 output Digital I/O, I2C Serial Data I/O Digital I/O, I2C Serial Clock General Reset Digital I/O Ports Ground Digital Ground 14/106 ST52F501L/F502L 1.3 Pin Description ST52F501L/F502L pins can be set in digital input mode, digital output mode, interrupt mode or in Alternate Functions. Pin configuration is achieved by means of the configuration registers. The functions of the ST52F501L/F502L pins are described below: VDD. Main Power Supply Voltage. VDDIO. I/O Ports Power Supply Voltage. It is reccomended to connect this pin with a supply voltage de-coupled with VDD in order to improve the immunity from the noise generated by the I/O switching (only 32 pin packages). VSS. Digital circuit Ground. VSSIO. I/O Ports Ground. See VDDIO VPP. Programming/Working mode selector. During the Programming phase VPP must be set to VDD. In Working phase VPP must be equal to VSS. OSCin and OSCout. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal or a ceramic resonator can be connected between these two pins in order to allow correct use of ST52F501L/F502L with various stability/ cost trade-offs. An external clock signal can be applied to OSCin: in this case OSCout must be grounded. To reduce costs, an RC circuit can be applied to the OSCin pin to establish the internal clock frequency, instead of the quartz. Without any connection, the device can work with its internal clock generator (10 MHz) RESET. This signal is used to reset the ST52F501L/F502L and re-initialize the registers and control signals. It is also used when switching from the Programming Mode to Working Mode and vice versa. PA0-PA7, PB0-PB7,PC0-PC7. These lines are organized as I/O ports. Each pin can be configured as an input, output (with pull-up, push-pull, weakpull-up, open-drain, high-impedance), or as an interrupt source. T0OUT, T1OUT. These pins output the signals generated by the PWM/Timer 0 and PWM/Timer 1 peripheral. TRES, TSTRT, TCLK. These pins are related to the PWM/Timer 0 peripheral and are used for Input Capture and event counting. The TRES pin is used to set/reset the Timer; the TSTRT pin is used to start/stop the counter. The Timer can be driven by the internal clock or by an external signal connected to the TCLK pin. INT. This pin is used as input for the Non-Maskable (top level) interrupt. The interrupt signal is detected only if the pin is configured in Alternate Function. SCL, SDA. These pin are used respectively as Serial Clock and Serial Data I/O in I2C peripheral protocol. They are used also in Programming Mode to receive and transmit data. SCK, MISO, MOSI, SS. These pins are used by the Serial Peripheral Interface (SPI) peripheral. SCK is the serial clock line. MISO (Master In Slave Out) and MOSI (Master Out Slave In) are the serial data lines, which work in input or in output depending on if the device is working in slave or master mode. The SS pin allows the selection of the device master/slave mode. TX, RX. Serial data output of SCI Transmitter block (TX) and Serial data input of the SCI Receiver block (RX). 15/106 ST52F501L/F502L 2 ADDRESSING SPACES ST52F501L/F502L has six separate addressing spaces: s Register File s s s s s Program/Data Memory Stacks Input Registers Output Registers Configuration Registers Each space is addressed by a load type instruction that indicates the source and the destination space in the mnemonic code (see Figure 2.1). 2.1 Memory Interface The read/write operation in the space addresses are managed by the Memory Interface, which can recognize the type of memory addressed and set the appropriate access time and mode. In addition, the Memory Interface manages the In Application Programming (IAP) functions in Flash devices like writing cycle and memory write protection. Figure 2.1 Addressing Spaces 2.2 Register File The Register File consists of 256 general purpose 8-bit RAM locations called "registers" in order to recall the functionality. The Register File exchanges data with all the other addressing spaces and is used by the ALU to perform all the arithmetic and logic instructions. These instructions have any Register File address as operands. Data can be moved from one location to another by using the LDRR instruction; see further ahead for information on the instruction used to move data between the Register File and the other addressing spaces. 2.3 Program/Data Memory The Program/Data Memory consists of both nonvolatile memory (Flash, EEPROM) and RAM memory benches. Non-volatile memory (NVM) is mainly used to store the user program and can also be used to store permanent data (constant, look-up tables). Each RAM bench consists of 256 locations used to store run-time user data. At least one bench is present in the devices. RAM benches are also used to implement both System and User Stacks. STFive CORE PROGRAM/DATA MEMORY REGISTER FILE NON VOLATILE MEMORY LDER LDFR DECISION PROCESSOR REGISTERS ON CHIP PERIPHERALS OUTPUT REGISTERS LDPR PERIPHERAL BLOCK LDCNF LDRE GETPG PGSETR RAM BANKS AND STACKS PROGRAM COUNTER INPUT REGISTERS LDCR CU DPU ALU CONFIGURATION REGISTERS PERIPHERAL BLOCK LDRI PERIPHERAL BLOCK LDCE LDPE 16/106 ST52F501L/F502L NVM is always located beginning after the first locations of the addressing space. RAM banks are always located after NVM. NVM is organized in accordance to the following blocks (see Figure 2.2): s Reset Vector block (from address 0 to 2) contains an absolute jump instruction to the first user program instruction. The Assembler tool automatically fills these locations with correct data. s s Mbfs Setting block (just after the interrupt vectors) contains the coordinates of the vertexes of every Mbf defined in the program. The last address that can be assigned to this block is 1023. This area is dynamically assigned according to the size of the fuzzy routines. The memory area that remains unused, if any, is assigned to the Program Instructions block. The Program Instructions block (just after the last Mbf data through the last NVM address) contains the instruction of the user program and the permanent data. Option bytes block (from location 3000h to 307Fh) is the addressing space reserved for the option bytes. In ST52F501L/F502L, only the location from 3000h to 3007h are used. s Interrupt Vectors block (from location 3 up to 32) contains the interrupt vectors. Each address is composed of three bytes (the jump opcode and the 16 bit address). Interrupt vectors are set by using IRQ pseudo-instruction (see the Programming Manual). s Figure 2.2 Program/Data Memory Organization FFFFh ~ 307Fh OPTION BYTES ~ SPACE NOT ADDRESSABLE 3000h ~ 20FFh SYSTEM STACK DATA USER STACK ~ RAM BENCH 2000h PROGRAM INSTRUCTIONS AND PERMANENT DATA NON VOLATILE MEMORY 0400h PROGRAM INSTRUCTIONS AND PERMANENT DATA MEMBERSHIP FUNCTIONS PARAMETERS 0021h INTERRUPT VECTORS 0003h RESET VECTOR 0000h 17/106 ST52F501L/F502L Flash and EEPROM are programmed electrically just applying the supply voltage and it is also erased electrically; this feature allows the user to easily reprogram the memory without taking the device off from the board (In Situ Programming ISP). Data and commands are transmitted through the I2C serial communication protocol. Data can also be written run-time with the In Application Programming (IAP) NVM can be locked by the user during the programming phase, in order to prevent external operation such as reading the program code and assuring protection of user intellectual property. Flash and EEPROM pages can be protected by unintentional writings. The operations that can be performed on the NVM during the Programming Phase, ISP and IAP are described in detail in the Section 4. Figure 2.3 System and User Stack 2.4 System and User Stacks The System and User Stacks are located in the Program/Data memory in the RAM benches. System Stacks are used to push the Program Counter (PC) after an Interrupt Request or a Subroutine Call. After a RET (Return from a subroutine) or a RETI (Return from an interrupt) the PC that is saved is popped from the stack and restored. After an interrupt request, the flags are also saved in a reserved stack inside the core, so each interrupt has its own flags. The System Stack is located in the last RAM bench starting from the last address (255) inside the bench page. The System Stack Pointer (SSP) can be read and modified by the user. For each level of stack 2 bytes of the RAM are used. The SSP points to the first currently available stack position. When a subroutine call or interrupt request occurs, the content of the PC is stored in a couple of locations pointed to by the SSP that is decreased by 2. RAM BENCH 20FFh 20FEh PROGRAM COUNTER SYSTEM STACK RETI LEVEL 1 SYSTEM STACK PAGE NUMBER MSB LOCATION ADRESS LSB SYSTEM STACK POINTER LEVEL 2 SYSTEM STACK LEVEL 3 SYSTEM STACK LEVEL 4 IRQ REGISTER FILE POP X USER DATA REGISTER X CONFIGURATION REGISTERS USER STACK POINTER USER STACK LEVEL 4 USER STACK LEVEL 3 USER STACK LEVEL 2 USER STACK LEVEL 1 PUSH X USER STACK TOP LSB USER STACK TOP MSB 2001h 2000h 18/106 ST52F501L/F502L When a return occurs (RET or RETI instruction), the SSP is increased by 2 and the data stored in the pointed locations couple is restored back into the PC. The current SSP can be read and write in the couple of Configuration Registers 44 02Ch (MSB: page number, always 32 020h) and 45 02Dh (LSB: location address) (see Figure 2.3). In ST52F501L/ F502L the user can only consider the LSB because the MSB is always the same. The User Stack is used to store user data and is located beginning from a RAM bench location set by the user (USTP) by writing the couple of Configuration Registers 5 005h (MSB: page number) and 6 005h (LSB: location address) (see Figure 2.3). Register 5, which is the page number, must always be set to a value between 32 (020h) and 255 (0FFh): values higher than 32 always address RAM on page 32. This feature allows a flexible use of the User Stack in terms of dimension and to avoid overlaps. The User Stack Pointer (USP) points to the first currently available stack location. When the user stores a byte value contained in the Register File by using the PUSH instruction, the value is stored in the position pointed to by the USP that is increased (the User Stack order is opposite to the System Stack one). When the user takes a value from the User Stack with the POP instruction, the USP is decreased and the value pointed to is copied in the specified Register File location. By writing the USTP, the new address is automatically written in the USP. The current USP can be read from the Input Registers 11 0Bh (MSB: page number, always 32 020h) and 12 0Ch (LSB: location address) (see Figure 2.3). In ST52F501L/ F502L the user can only consider the LSB because the MSB is always the same. further details on this instruction. The Input Registers are read-only registers. In order to simplify the concept, a mnemonic name is assigned to each register. The list of the Input Registers is shown in Table 2.1. 2.6 Output registers The ST52F501L/F502L Output Registers bench consists of a file of 8-bit registers containing data sent to the Peripherals and the I/O Ports (for example: Timer Counters, data to be transmitted by the serial communication peripherals, data to be sent to the Port pins in output, etc.). The registers are located inside the Peripherals and Ports, which allow flexibility and modularity in the design of new family devices. The Output Registers are write only. In order to access the configuration Register the user can use the following instructions: s LDPI: loads the immediate value in the specified Output Register. s LDPR: loads the contents of the specified Register File location into the output register specified. This instruction allows computed data to be sent to Peripherals and Ports. LDPE direct: loads the contents of the specified Program/Data Memory location into the output register specified. This instruction allows data to be sent to Peripherals and Ports from a table. LDPE indirect: loads the contents of the Program/Data Memory location whose address is contained in the specified Register File location into the output register specified. This instruction allows data to be sent to Peripherals and Ports from a table pointed to by a register. s s Note: The user must pay close attention to avoid overlapping user and Stacks data. The User Stack Top location and the System Stack Pointer should be configured with care in order to have enough space between the two stacks. 2.5 Input Registers The ST52F501L/F502L Input Registers bench consists of a file of 8-bit registers containing data or the status of the peripherals. For example, the Input Registers contain data converted by the ADC, Ports, serial communication peripherals, Timers, etc. The Input Registers can be accessed by using the LDRI instruction that loads the specified Register File address with the contents of the specified Input Register. See the Programming Manual for See the Programming manual for further details about these instructions. In order to simplify the concept, a mnemonic name is assigned to each register. The list of the Output Registers is shown in Table 2.2. 2.7 Configuration Registers & Option Bytes The ST52F501L/F502L Configuration Registers bench consists of a file of 8-bit registers that allows the configuration of all the ICU blocks. The registers are located inside the block they configure in order to obtain greater flexibility and modularity in the design of new family devices. In the Configuration Registers, each bit has a peculiar use, so the logic level of each of them must be considered. 19/106 ST52F501L/F502L Some special configuration data, that needs to be load at the start-up and not further changed, are stored in Option Bytes. These are loaded only during the device programming phase. See Table 2.3 and Section 4 for a detailed description of the Option Bytes. The Configuration Registers are readable and writable; the addresses refer to the same register both in read and in write. In order to access the Configuration Register the user can work in several modes by utilizing the following instructions: s LDCI: loads the immediate value in the Configuration Register specified and is the most commonly used to write configuration data. s Register File location, allowing a parametric configuration. s LDCE: loads the Configuration Register specified with the contents of the specified Program/Data Memory location, allowing the configuration data to be taken from a table. LDCNF: loads the Register File location specified with the contents of the Configuration Register indicated, allowing for the inspection of the configuration of the device (permitting safe run-time modifications). s LDCR: loads the Configuration Register specified with the contents of the specified In order to simplify the concept, a mnemonic name is assigned to each register. The list of the Configuration Registers is shown in Table 2.4. 20/106 ST52F501L/F502L Table 2.1 Input Registers Mnemonic PORT_A_IN PORT_B_IN PORT_C_IN SPI_IN I2C_IN I2C_SR1 I2C_SR2 USP_H USP_L PWM0_COUNT_IN PWM0_STATUS PWM0_CAPTURE PWM1_COUNT_IN PWM1_STATUS PWM1_CAPTURE SCI_IN SCI_STATUS FLAGS IAP_SR Description Port A data Input Register Port B data Input Register Port C data Input Register Not Used Serial Peripheral Interface data Input Register I2C Interface data Input Register I2C Interface Status Register 1 I2C Interface Status Register 2 Not Used Not Used User Stack Pointer (MSB) User Stack Pointer (LSB) Not Used PWM/Timer 0 Counter Input Register PWM/Timer 0 Status Register Not Used PWM/Timer 0 Capture Input Register Not Used PWM/Timer 1 Counter Input Register PWM/Timer 1 Status Register Not Used PWM/Timer 1 Capture Input Register Not Used Serial Communication Interface RX data Input Register Serial Communication Interface Status Register Flag Register Not Used Programmable Low Voltage Detector and In Application Programming Status Register Not Used 0 1 2 3-4 5 6 7 8 9 10 11 12 13-21 22 23 24 25 26 27 28 29 30 31-35 36 37 38 39 40 41-56 Address 00h 01h 02h 03h-04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh-015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh-023h 024h 025h 026h 027h 028h 029h-038h 21/106 ST52F501L/F502L Table 2.2 Output Registers Mnemonic PORT_A_OUT PORT_B_OUT PORT_C_OUT SPI_OUT I2C_OUT PWM0_COUNT_OUT PWM0_RELOAD PWM1_COUNT_OUT PWM1_RELOAD SCI_OUT Description Port A data Output Register Port B data Output Register Port C data Output Register Not Used Serial Peripheral Interface data Output Register I2C Interface data Output Register Not Used PWM/Timer 0 Counter Output Register Not Used PWM/Timer 0 Reload Register Not Used PWM/Timer 1 Counter Output Register Not Used PWM/Timer 1 Reload Register Not Used Serial Communication Interface TX data Output Register 0 1 2 3-4 5 6 7 8 9 10 11 12 13 14 15-22 23 Address 00h 01h 02h 03h-04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh-016h 017h Table 2.3 Option Bytes Mnemonic OSC_CR CLK_SET OSC_SET PLVD_SET WDT_EN PG_LOCK PG_UNLOCK WAKEUP Description Oscillator Control Register Clock Parameters Oscillator Set-Up PLVD and PDR Set-Up Register HW/SW Watchdog selector First Page Write Protected First Page not Write Protected Wake Up from Halt Time 0 1 2 3 4 5 6 7 Address 00h 01h 02h 03h 04h 05h 06h 07h 22/106 ST52F501L/F502L Table 2.4 Configuration Registers Mnemonic INT_MASK INT_POL INT_PRL_H INT_PRL_M INT_PRL_L USTP_H USTP_L WDT_CR PWM0_CR1 PWM0_CR2 PWM0_CR3 PWM1_CR1 PWM1_CR2 I2C_CR I2C_CCR I2C_OAR1 I2C_OAR2 SPI_CR SPI_STATUS_CR SCI_CR1 SCI_CR2 PORT_A_PULLUP PORT_A_OR PORT_A_DDR Description Interrupt Mask Register Interrupts Polarity Interrupt Priority Register (higher priority) Interrupt Priority Register (medium priority) Interrupt Priority Register (lower priority) User Stack Top Pointer (MSB) User Stack Top Pointer (LSB) Watchdog Configuration Register not used PWM/Timer 0 Configuration Register 1 PWM/Timer 0 Configuration Register 2 PWM/Timer 0 Configuration Register 3 PWM/Timer 1 Configuration Register 1 PWM/Timer 1 Configuration Register 2 Not Used I2C Interface Control Register I2C Interface Clock Control Register I2C Interface Own Address Register 1 I2C Interface Own Address Register 2 Serial Peripheral Interface Control Register Serial Peripheral Interface Control-Status Register Serial Communication Interface Control Register 1 Serial Communication Interface Control Register 2 Port A Pull Up enable/disable Register Port A Option Register Port A Data Direction Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14-15 16 17 18 19 20 21 22 23 24 25 26 Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh-0Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 23/106 ST52F501L/F502L Table 2.4 Configuration Registers Mnemonic PORT_A_AF PORT_B_PULLUP PORT_B_OR PORT_B_DDR PORT_B_AF PORT_C_PULLUP PORT_C_OR PORT_C_DDR PORT_C_AF SCI_CR3 SSP_H SSP_L CPU_CLK IR_CR1 IR_CR2 PWM_LU_CR PLVD_CR PHW_CR Description Port A Alternate Function selection Register Port B Pull Up enable/disable Register Port B Option Register Port B Data Direction Register Port B Alternate Function selection Register Port C Pull Up enable/disable Register Port C Option Register Port C Data Direction Register Port C Alternate Function selection Register Not Used Serial Communication Interface Control Register 3 System Stack Pointer (MSB) System Stack Pointer (LSB) CPU Clock Prescaler Not Used IR Driver Control Register 1 IR Driver Control Register 2 PWM/Timers' Logic Unit Control Register Programmable Low Voltage Detector (PLVD) Programmable Halt Wake-up Control Register 27 28 29 30 31 32 33 34 35 36-42 43 44 45 46 47 48 49 50 51 52 Address 01Bh 01Ch 01Dh 01Eh 01Fh 020h 021h 022h 023h 024h-02Ah 02Bh 02Ch 02Dh 02Eh 02Fh 030h 031h 032h 033h 034h 24/106 ST52F501L/F502L 3 INTERNAL ARCHITECTURE ST52F501L/F502L's architecture is Register File based and is composed of the following blocks and peripherals: s Control Unit (CU) s s s s s s s s s s s s s s s s s Data Processing Unit (DPU) Decision Processor (DP) ALU Memory Interface up to 256 bytes Register File Program/Data Memory Data EEPROM Interrupts Controller Clock Oscillator PLVD, PDR and POR Digital I/O ports Timer/PWM Timer/PWM with IR Driver I2C SPI SCI PHW 3.1 Control Unit and Data Processing Unit The Control Unit (CU) decodes the instructions stored in the Program Memory and generates the appropriate control signals. The main parts of the CU are illustrated in Figure 3.1. The five different parts of the CU manage Loading, Logic/Arithmetic, Jump, Control and the Fuzzy instruction set. The block called "Collector" manages the signals deriving from the different parts of the CU. The collector defines the signals for the Data Processing Unit (DPU) and Decision Processor (DP), as well as for the different peripherals of the ICU. The block called "Arbiter" manages the different parts of the CU, so that only one part of the system is activated during working mode. The CU structure is extremely flexible and was designed with the purpose of easily adapting the core of the microcontroller to market needs. New instruction sets or new peripherals can easily be included without changing the structure of the microcontroller, maintaining code compatibility. A set of 107 different instructions is available. Each instruction requires a number of clock pulses to be performed that depends on the complexity of the instruction itself. The clock pulses to execute the instructions are driven directly by the masterclock, which has the same frequency of the oscillator signal supplied. Figure 3.1 CU Block Diagram MicroCode Loading Instruction Set A R B I T E R Logic Arithmetic Instruction Set Jump Instruction Set Control Instruction Set C O L L E C T O R Control Signals Clock Master Decision Processor Instruction Set 25/106 ST52F501L/F502L Figure 3.2 Data Processing Unit (DPU) Interrupts Unit PROGRAM COUNTER Memory Address Program Memory Input Registers Peripherals Control Unit Peripherals REGISTER FILE REGISTER FILE ADDRESS 256 Bytes DECISION PROCESSOR REGISTERS ACCUMULATOR FLAGS REG. ALU The DPU receives, stores and sends the instructions deriving from the Program/Data Memory, Register File or from the peripherals. It is controlled by the CU on the basis of the decoded instruction. The Fuzzy registers store the partial results of the fuzzy computation. The accumulator register is used by the ALU and is not accessible directly: the instructions used by the ALU can address all the Register File locations as operands, allowing a more compact code and a faster execution. The following addressing modes are available: inherent, immediate, direct, indirect, bit direct. 3.1.1 Program Counter. The Program Counter (PC) is a 16-bit register that contains the address of the next memory location to be processed by the core. This memory location may be both an instruction or data address. The Program Counter's 16-bit length allows the direct addressing of a maximum of 64 Kbytes in the Program/Data Memory space. The PC can be changed in the following ways: s JP (Jump) PC = Jump Address s s s s s s Interrupt RETI RET CALL Reset Normal Instruction PC = Interrupt Vector PC = Pop (stack) PC = Pop (stack) PC = Subroutines address PC = Reset Vector PC = PC + 1 3.1.2 Flags. The ST FIVE core includes different sets of flags that correspond to 2 different modes: normal mode and interrupt mode. Each set of flags consist of a CARRY flag (C), ZERO flag (Z) and SIGN flag (S). Each set is stacked: one set of flags is used during normal operation and other sets are used during each level of interrupt. Formally, the user has to manage only one set of flags: C, Z and S since the flag stack operation is performed automatically. 26/106 ST52F501L/F502L Each interrupt level has its own set of flags, which is saved in the Flag Stack during interrupt servicing. These flags are restored from the Flag Stack automatically when a RETI instruction is executed. If the ICU was in normal mode before an interrupt, after the RETI instruction is executed, the normal flags are restored. 3.2 Arithmetic Logic Unit The 8-bit Arithmetic Logic Unit (ALU) performs arithmetic calculations and logic instructions such as: sum, subtraction, bitwise AND, OR, XOR, bit set and reset, bit test and branch, right/left shift and rotate (see the Chapter 9 Instruction Set for further details). In addition, the ALU of ST52F501L/F502L can perform multiplication (MULT) and division (DIV). Multiplication is performed by using 8 bit operands storing the result in 2 registers (16 bit values); the division instruction addresses the MSB of the dividend (the LSB is stored in the next address): the result and remainder are stored in these source addresses (see Figure 3.3 and Figure 3.4). In order to manage signed type values, the ALU also performs addition and subtraction with offset (ADDO and SUBO). These instructions respectively subtract and add 128 to the overall result, in order to manage values logically in the range between -128,127. Note: A subroutine CALL is a normal mode execution. For this reason a RET instruction, consequent to a CALL instruction, doesn't affect the normal mode set of flags. Flags are not cleared during context switching and remain in the state they were in at the exit of the last interrupt routine switching. The Carry flag is set when an overflow occurs during arithmetic operations, otherwise it is cleared.The Sign flag is set when an underflow occurs during arithmetic operations, otherwise it is cleared. The flags, related to the current context, can be checked by reading the FLAGS Input Register 38 (026h). Figure 3.3 Multiplication Figure 3.4 Division RAM 000h 001h 002h 000h 001h 002h RAM i-1 i i i+1 j-1 j j+1 j-1 j j+1 0FDh 0FEh 0FFh 0FDh 0FEh 0FFh REG. j X 16 Bit REG. i REG. j REG. j+1 : REG. i LSB MSB REMAINDER QUOTIENT 27/106 ST52F501L/F502L 3.3 Register Description Flags Register (FLAG) Input Register 38 (026h) Read Only Reset Value: 0000 0000 (00h) 7 Z S 0 C Bit 7-3: Not Used Bit 2: Z Zero flag Bit 1: S Sign flag Bit 0: C Carry flag 28/106 ST52F501L/F502L 4 MEMORY PROGRAMMING ST52F501L/F502L provides an on-chip user programmable non-volatile memory, which allows fast and reliable storage of user data. Program/Data Memory addressing space is composed by a Single Voltage Flash Memory and a RAM memory bench. The ST52F502L devices also have a Data EEPROM bench to store permanent data with long term retention and a high number of write/erase cycles. All the Program Data memory addresses can execute code, including RAM and EEPROM benches. The memory is programmed by setting the Vpp pin equal to Vdd. Data and commands are transmitted through the I2C serial communication protocol. The same procedure is used to perform "In-Situ" the programming of the device after it is mounted in the user system. Data can also be written in runtime with the In-Application Programming (IAP). The Memory can be locked by the user during the programming phase, in order to prevent external operation such as reading the program code and assuring protection of user intellectual property. Table 4.1 Sales Types Memory Organization Flash Memory Device Amount ST52F501Lx1x6 ST52F501Lx2x6 ST52F501Lx3x6 ST52F502Lx1x6 ST52F502Lx2x6 ST52F502Lx3x6 2048 bytes 4096 bytes 8192 bytes 1792 bytes 3840 bytes 7936 bytes Pages 0 to 7 0 to 15 0 to 31 0 to 6 0 to 14 0 to 30 Amount 256 bytes 256 bytes 256 bytes 256 bytes 256 bytes 256 bytes Page 32 32 32 32 32 32 Amount 256 bytes 256 bytes 256 bytes Page 7 15 31 RAM Memory EEPROM Memory Flash and EEPROM pages can be protected by unintentional writings. Remark: the memory contents are protected by the Error Correction Code (ECC) algorithm that uses a 4-bit redundancy to correct one bit errors. 4.1 Program/Data Memory Organization The Program/Data Memory is organized as described in Section 2.3. The various sales types have different amounts of each type of memory. Table 4.1 describes the memory benches amount and page allocation for each sales type. The addressing spaces are organized in pages of 256 bytes. Each page is composed by blocks of 32 bytes. Memory programming is performed one block at a time in order to speed-up the programming time (about 2.5 ms per block). The whole location address is composed as follows: 15 Page address 8 7 5 4 0 Block address address inside the block Legend: c: Y=16 pins, F=20 pins, G=28 pins, K=32/34 pin p: B=DIP, M=SO, T=TQFP 29/106 ST52F501L/F502L 4.2 Memory Programming The Programming procedure writes the user program and data into the Flash Memory, EEPROM and Option Bytes. The programming procedures are entered by setting the Vpp pin equal to Vdd and releasing the Reset signal. The following pins are used in Programming mode: s VPP used to switch to programming mode s s s s s 1. 2. 3. 4. 5. 6. 7. VPP is set to VDD The device is Reset (RESET=VSS) The Reset is released (RESET=VDD) The internal oscillator starts at 10 MHz The memory is turned on The I2C Interface and Ports are initialized The I2C Interface is configured to work as Slave, Receiver, 7-bit address and waits for data The Start signal is sent to the chip followed by the Slave Address 1010000 and the direction bit set to 0 (the addressed slave waits for data). The device sends the acknowledge The Programming Mode code 00000000 is sent and acknowledged VDD VSS RESET SCL SDA device supply device ground device reset I2C serial clock I2C serial data 8. During the device programming, the internal clock is used, so the OSCin and OSCout pins don't have to be considered. 4.2.1 Programming Mode start. The following sequence starts the Programming Mode: 9. 10. A command code is sent to the device 11. The procedure related to the command is executed Table 4.2 Programming Mode Commands Command BlockWrite Code 00000001 Data in 32 Data out Erase Yes Description Write the currently addressed block with the 32 bytes following the command. The Block locations are erased before being written. Write the byte addressed by the next data sent in the currently addressed page. Erase the block addressed by 3 MSB of the next data sent and inside the currently addressed page. Erase the byte addressed by the next data sent and inside the currently addressed page. Read the byte addressed by the next data sent and inside the current page. The read data is sent by the device after the re-send of the Slave Address with the R/W bit changed. All the memory is erased. Write the currently addressed block with the 32 bytes following the command. The Block locations aren't erased. The currently addressed page is set with the next data sent. Read N consecutive bytes starting from the memory location currently addressed. The read data is sent by the device after the command is acknowledged. The current memory absolute address is post-incremented. The current block address is incremented modulo 8 (address 0 follows after address 7 and the Page is postincremented) This command is followed by a status data byte. Mostly used in error condition and to check if the device is locked ByteWrite BlockErase ByteErase 00000010 00000011 00000100 2 1 1 - Yes Yes Yes ByteRead GlobalErase 00000101 00001001 1 32 1 1 - Yes No - FastBlockWrite 00001011 SetPage 00001100 ReadData 00001101 - N - IncBlock 00001111 - - - ReadStatus 00010011 - 1 - 30/106 ST52F501L/F502L Figure 4.1 Commands and Data Communication Sequences Programming mode start sequence S 10100000 A 00000000 A Command A Data1 A ..... DataN A P Execution of commands for writing data: Command A Data1 A ..... DataN A Command A Data1 A ..... DataN A P Execution of commands for reading data: Command A Address A P S 10100001 A Data read NA P S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge From Slave to Master From Master to Slave The generic procedure of commands execution, with the data communication in both directions is displayed in Figure 4.1. 5. After the device acknowledges the 32nd byte, it holds the SCL line until the parallel writing of the 32 byte is completed (about 2.5 ms) The Block Pointer is incremented by sending the IncBlock command The procedure is repeated from point 3 until there is data to be sent to the memory Remark: the Slave Address 1010000 must be sent after a Stop (i.e. each time the data direction changes, to specify the R/W bit). For example: if a command to send data to the device has been executed, a command for receiving data must be followed by the slave address and the R/W bit must be set to 1. The Programming Mode code doesn't need to be specified again. Warning: After entering the Programming Mode, the currently pointed address is the Page 48, Block 3, byte 0 (Lock Byte). The list of the available commands Programming Mode is showed in Table 4.2 in 6. 7. Note: the Block Pointer assumes values between 0 to 7 (there are 8 blocks in a page). When the Block Pointer is equal to 7, the IncBlock command puts this pointer to 0 and increments the Page Pointer. The Page Pointer, after page writing is completed, doesn't have to be incremented in the procedure above described. 4.2.3 Random data writing. A single byte can be written in a specified memory location by using the following procedure: 1. The Programming Mode is entered with the sequence described in Section 4.2.1 2. The SetPage command is sent, followed by the page number where the data should be written The ByteWrite command is sent followed by two bytes The first bytes that follows the ByteWrite command is the address inside the pointed page where the data must be written. The second byte is the data to be written The device held the SCL line low until the data is not stored in the memory (about 4.5 ms: 2 ms for erasing and 2.5 for writing) 4.2.2 Fast Programming procedure. The fastest way to program the device memory is the use of the FastBlockWrite command. The following procedure can be used to write the memory with a new program and new data, starting from the first memory location: 1. The Programming Mode is entered with the sequence described above 2. The memory is erased (all bits are put to 0) with the GlobalErase command. The device holds the SCL line low, releasing it after the command is completed (about 2 ms). This command also unlocks the device if locked. The FastBlockWrite command is sent and the device acknowledges it The 32 bytes of data to be written in the first memory Block are sent in a sequence. The device acknowledges each of them 3. 4. 3. 4. 5. 6. 31/106 ST52F501L/F502L A similar procedure can be used to write a single block: 1. The SetPage command is sent, followed by the page number where the data should be written 2. The IncBlock command is sent as many times as the block number inside the page (for example: to address the block 3 the IncBlock must be sent 3 times) The WriteBlock command is sent followed by the 32 data bytes to be written. After the 32th byte is sent, the device holds the SCL line low until all the data are not stored in the memory (about 4.5 ms: 2 ms for erasing and 2.5 for writing: the same time for a single byte) The commands ByteErase and BlockErase, used instead of ByteWrite and BlockWrite, erase (put all bit to 0) the specified memory location or block. 4.2.4 Option Bytes Programming. The Option Byte addresses cannot be accessed with a sequential procedure like the one described in Section 4.2.2. Actually, the pointers are automatically incremented up to the last block or address in page 31. A further increment sets all the pointers to 0. The Option Byte addresses (located at page 48, block 0, addresses 0-7) must be accessed with a direct addressing procedure as the one described in Section 4.2.3. If the Fast Programming procedure is used, it must be followed by a Random Block Writing procedure to program the Option Bytes. The other 24 bytes of the block can be written with dummy values or user values. The blocks 0, 1, 2 and 3 of Page 48 can be used for writing data as well (see Section 4.5) and for locking the device (see Section 4.4). 3. 4. The procedures described previously can be repeated as many time as needed, without exiting from Programming Mode or re-sending the Slave Address again. Figure 4.2 Programming Procedures Fast Programming Procedure S 10100000 A 00000000 A GlobalErase A FastBlockWrite A Data0 A ..... ..... Data31 A IncBlock A FastBlockWrite A ..... Data31 A ..... ..... Data31 A P Random Byte Writing Procedure ..... SetPage A Page Address A ByteWrite A Byte Address A Data A Command ..... Random Block Writing Procedure ..... SetPage A Page Address A IncBlock A ..... IncBlock A BlockWrite A Data0 A ..... ..... Data31 A Command ..... Option Byte Writing Procedure ..... SetPage A 00110000 A WriteBlock A Option Byte 0 A ..... Option Byte 7 A ..... ..... Dummy 0 A ..... Dummy 23 A P S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge From Slave to Master From Master to Slave 32/106 ST52F501L/F502L Figure 4.3 Reading and Erasing Procedures Fast Reading Procedure S 10100000 A 00000000 A ReadData A P S 10100001 A Data read A ..... ..... ReadData A Data read A ..... Data read NA P Random Byte Reading Procedure ..... SetPage A Page Address A ByteRead A Byte Address A P S 10100001 A ..... ..... Data read NA P S 10100000 A Command ..... Byte Erasing Procedure ..... SetPage A Page Address A ByteErase A Byte Address A Command ..... Block Erasing Procedure ..... SetPage A Page Address A BlockErase A Block Address (*) A Command ..... (*) Block address is specified by the 3 most significative bits of the whole given address (less significative bits are don't care) S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge From Slave to Master From Master to Slave 4.3 Memory Verify To verify the memory contents or just to read part of data stored in memory, the ByteRead and the ReadData command can be used. The first instruction needs the specification of the address; the second one allows the sequential reading of consecutive memory locations. Since the device is "Slave" for the I2C protocol, after receiving a command for reading, it must be configured as Slave Transmitter to send the data. In order to do so, the Slave Address (1010000) must be sent again with the R/W byte set to 1, as stated by the communication protocol. 4.3.1 Fast read procedure. The memory can be read sequentially by using the following procedure: 1. The Programming mode is entered with the sequence described in Section 4.2.1 2. 3. The pointers address the memory location 0 The ReadData command is sent and the device acknowledges it. 4. 5. The Master generates a Stop condition followed by a Start condition The Slave Address with the R/W byte set to 1 (10100001) is sent. The device receives the Slave Address and acknowledges it. The device sends the data to be read in the serial data line SDA. The current absolute address is post-incremented. The Master device send the acknowledge to read the contents of the next location. The sequence restarts from point 6 until the master not acknowledge the data read and generates a Stop condition, in order to stop the reading sequence. 6. 7. 8. Remark: for the same reasons explained in Section 4.2.4 the Option Bytes cannot be read with this procedure: they can be read with a direct addressing procedure as the one explained in the next section. 33/106 ST52F501L/F502L 4.3.2 Random data reading. To read a specified memory location, the following procedure should be used: 1. The Programming mode is entered with the sequence described in Section 4.2.1 2. The SetPage command is sent, followed to the page number where the data to be read is located The ByteRead command is sent, followed by an address inside the page The Master generates a Stop condition followed by a Start condition The Slave Address with the R/W byte set to 1 (10100001) is sent. The device receives the Slave Address and acknowledges it. The device sends the data to be read in the serial data line SDA. The Master device doesn't send the acknowledge and generates a stop condition. To send the next command, the Master should generate a Start condition followed by the Slave Address with the R/W byte set to 0 (10100000). 4.4 Memory Lock The Program/Data Memory space can be locked to inhibit the reading of contents and protect the intellectual property. To lock the device, the user must set all the bit of the Lock Byte to `1'. The Lock Byte is located on Page 48 (030h), Block 3, byte 0 inside the block i.e. byte 96 (060h) inside the page. After writing 255 (0FFh) into the Lock Byte, with the procedure described in the Section 4.2.3, the memory is locked and the only command allowed are the following: - GlobalErase: this command, writing `0' in all the memory, also unlock the device. - ReadData: the only block that can be read is the Block 3 in Page 48 (030h); this allows the reading of the Lock Byte and the ID Code locations (see Section 4.5). - ReadStatus: this command allows the detection of an error condition in Programming mode operation (see Section Note:). It can also be used to check if the device is locked. The most significative bit return the Lock Bit (0=unlocked, 1=locked). 3. 4. 5. 6. 7. 8. Remark: the Lock Byte is checked when entering the Programming Mode. For this reason after writing the Lock Byte, all the commands can be carried out until the Programming mode is exited. Figure 4.4 Device Lock Procedure Device Lock Procedure ..... SetPage A 00110000 A ByteWrite A 01100000 A 11111111 A Command ..... Device Lock and ID Code Writing Procedure ..... SetPage A 00110000 A IncBlock A IncBlock A IncBlock A BlockWrite A ..... ..... 11111111 A ID Code 1 A ID Code 2 A ..... ID Code 31 A Command ..... Device Lock Reading Procedure ..... ReadStatus A P S 10100001 A Status Byte (*) NA P S 10100000 A Command ..... (*) The most significative bit return the Lock Bit (0=unlocked, 1=locked) S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge From Slave to Master From Master to Slave 34/106 ST52F501L/F502L Figure 4.5 Error Handling Procedure Wrong command/data case handling: Wrong Command/Data A Command/Data NA ReadStatus A P S 10100001 A Status Byte NA P S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge From Slave to Master From Master to Slave When the device is locked, if memory reading is attempted, with the exception of the Lock Byte and ID Code block, the device returns no data and an error sequence. If memory writing is attempted in any memory location, the device doesn't carry out the command and returns an error sequence. To unlock the device the GlobalErase command must be executed before any writing or reading command. 4.5 ID Code Block 3 on Page 48 (030h) can also be read if the device is locked. The first byte of the block is the Lock Byte, the other 31 locations are available to the user for writing data, as for example identification codes to distinguish the firmware version loaded in the device. The ID Code must be written before locking the device: after the device is locked it can only be read. The use of the Block writing procedure is the fastest way: the ID Code is written together the Lock Byte, which is sent first, then the 31 bytes of ID Code follow. The blocks 0, 1 and 2 on Page 48 can be also be used for writing data, but they cannot be accessed when the device is locked. 4.6 Error cases If a wrong command or data is sent to the device, it generates an error condition by not sending the acknowledge after the first successive data or command. Figure 4.5 shows the error sequence. The error case can be handled by using the ReadStatus command. This command can be sent after the error condition is detected; the device returns a Status Byte containing the error code. The ReadStatus command sequence is showed in Figure 4.5. The list of the error codes is illustrated in Table 4.3. Remark: after the ReadStatus command execution or after any error, the Start Sequence must be carried out before sending a new command. The Most Significative Bit of the error codes indicates (when set to `1') that the memory is locked. When a command, that is not allowed when the memory is locked, is sent, the "Not Allowed" code is sent. If another code is sent with the MSB to `1' it indicates that the error condition is not caused by the memory lock, but by the event related with the code sent. Note: the ID Code cannot be modified if the device is locked: it can only be read. Table 4.3 Error codes Name Device Locked Wrong Direction Stop Missed Data Missing Receive Error Wrong Command Not Allowed Wrong Mode Code xyyyyyyy x0000001 x0000010 x0000011 x0000100 x0000101 x0000110 x0010000 Warning: when the data writing into a non existing location is attempted, no error condition is generated. The user must take care in specifying the correct page address. Description x=lock bit (1=device locked), yyyyyyy=error code A transmit direction, not correct in the running sequence, has been set The Master missed generating a necessary Stop Condition The Master missed to send necessary data to the device The data sent by the Master hasn't been received correctly by the device The Master sent a wrong command code A command not allowed when the device is locked has been sent A code different form the Programming mode code (00000000) has been sent 35/106 ST52F501L/F502L 4.7 In-Situ Programming (ISP) The Program/Data Memory can be programmed using the ISP mode. This mode allows the device to be programmed when it is mounted in the user application board. This feature can be implemented by adding a minimum number of components and board impact. The programming procedures and pins used are identical to the ones described before for the standard Programming Mode. All the features previously described in this chapter are applicable in ISP mode. If RESET, SCL and SDA pins are used in the user application board for other purposes, it is recommended to use a serial resistor to avoid a conflict when the other devices force the signal level. The ISP can be applied by using the standard tools for the device programming. The ST52F501L Starter Kit supplies a cable to perform the ISP. The user application board should supply a suited connector type for the cable (see Starter Kit User Manual). 4.8.2 Block write. This procedure allows the writing of 32 bytes in parallel. These bytes should belong to the same block. Before the writing in the Program/Data memory, data must be buffered in the Register File in the first 32 locations (0-31, 00h-020h) by using the normal instructions to load the Register File locations. Then the data writing starts by using the BLKSET instruction. The destination block is addressed by specifying the memory page with the PGSET or PGSETR instruction before to start the writing; the block inside the page is addressed with the argument of the BLKSET instruction. Example: PGSET 5 BLKSET 4 This instruction sequence writes the contents of the first 32 bytes of the Register File in the locations 1408-1439 (0580h-059Fh). Warning: the user should be careful in specifying the correct page and block: the addressing of an not existing block can cause the unwanted writing of a different block. As soon as the BLKSET instruction is executed, the data writing starts and is performed in about 4.5 ms. This procedure may also be used to write few data, taking in account that all the 32 byte are written in the block anyway. 4.8.3 Memory Corruption Prevention. The user can protect some pages (or all the memory) from unintentional writings. The only constraint is that the protected pages must be consecutive. Two Option Bytes allow the specification of the page to be protected: PG_LOCK (Option Byte 5) and PG_UNLOCK (Option Byte 6). PG_LOCK is used to specify the first protected page; PG_UNLOCK is used to specify the first page not protected after the protected ones. The pages between the two addresses are protected. When writing in a protected page is attempted, the procedure is aborted and the bit PRTCD of IAP_SR Input register is set. If the PG_LOCK and PG_UNLOCK have the same value, no page is protected. By default, the two Option Bytes are programmed with the value 0, so the memory is not write protected by default. In Programming Mode the protection is not considered and the pages can be written unless the device is locked. 4.8 In-Application Programming (IAP) The In Application Programming Mode (IAP) allows the writing of user data in the Flash and EEPROM memories when the user program is running. There are two ways to write data in IAP mode: single byte write and Block write. Both procedures take about 4.5 ms to complete the writing: the Block write allows the writing of 32 byte in parallel. Remark: during data writing, the execution of the user program is stopped until the procedure is completed. Interrupt requests stop the writing operation and the data may be not stored. The bit ABRT in the IAP_SR Input register signals that the data writing hasn't been completed. To assure writing completion, the user should globally disable the interrupts (UDGI instruction) before starting IAP data writing. 4.8.1 Single byte write. Writing of a single byte in the Non-Volatile Program/Data memory is performed by using the LDER instruction (both direct and indirect addressing). The memory page should be indicated before the LDER instruction with the PGSET or PGSETR instruction. The byte address inside the page is specified by the LDER instruction itself. As soon as the instruction is executed, the data writing starts and is performed in about 4.5 ms. 36/106 ST52F501L/F502L 4.8.4 Option Bytes. First Protected Page (PG_LOCK) Option Byte 5 (05h) Reset Value: 0000 0000 (00h) 7 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 4.8.5 Input Register. IAP Status Register (IAP_SR) Input Register 40 (028h) Read only Reset Value: 0000 0000 (00h) 0 LCK0 7 PLVDST PRTCD 0 ABRT Bit 7-0: LCK7-0 First Page write protected In this register the address of first page to be protected in writing is specified. The pages following this one are protected up to the page specified by the PG_UNLOCK Option Byte (not included among the protected ones). Bit 7: See Section 6.6.3 Bit 6-2: Not Used Bit 1: PRTCD Page Protected 0: The writing has been completed 1: The writing has been aborted because the page is protected. Bit 0: ABRT Writing operation aborted 0: The writing has been completed 1: The writing has been aborted because an interrupt or another unspecified cause occurred. The ABRT and PRTCD bits are reset after the next successful data writing in the Flash of EEPROM memory. First Page not Protected (PG_UNLOCK) Option Byte 6 (06h) Reset Value: 0000 0000 (00h) 7 0 UNLCK7 UNLCK6 UNLCK5 UNLCK4 UNLCK3 UNLCK2 UNLCK1 UNLCK0 Bit 7-0: UNLCK7-0 First Page not write protected In this register the address of first page not write protected after the protected ones is specified. The pages following this one aren't protected. 37/106 ST52F501L/F502L 5 INTERRUPTS The Control Unit (CU) responds to peripheral events and external events through its interrupt channels. When such events occur, if the related interrupt is not masked and doesn't have a priority order, the current program execution can be suspended to allow the CU to execute a specific response routine. Each interrupt is associated with an interrupt vector that contains the memory address of the related interrupt service routine. Each vector is located in the Program/Data Memory space at a fixed address (see Figure 2.2 Program/Data Memory Organization). 5.1 Interrupt Processing If interrupts are pending at the end of an arithmetic or logic instruction, the interrupt with the highest priority is acknowledged. When the interrupt is acknowledged the flags and the current PC are saved in the stacks and the associated Interrupt routine is executed. The start address of this routine (Interrupt Vector) is located in three bytes of the Program/Data Memory between address 3 and 32 (03h-020h). See Table 5.1 for the list of the Interrupt Vector addresses. The Interrupt routine is performed as a normal code. At the end of each instruction, the CU checks if a higher priority interrupt has sent an interrupt request. An Interrupt request with a higher priority stops lower priority Interrupts. The Program Counter and the flags are stored in their own stacks. With the instruction RETI (Return from Interrupt) the flags and the Program Counter (PC) are restored from the top of the stacks. These stacks have already been described in Paragraph 2.4. An Interrupt request cannot stop fuzzy rule processing, but only after the end of a fuzzy rule or at the end of a logic or arithmetic instruction, unless a Global Interrupt Disable instruction has been executed before (see below). Figure 5.1 Interrupt Flow NORMAL PROGRAM FLOW INTERRUPT SERVICE ROUTINE INTERRUPT RETI INSTRUCTION 5.2 Global Interrupt Request Enabling When an Interrupt occurs, it generates a Global Interrupt Pending (GIP). After a GIP a Global Interrupt Request (GIR) will be generated and Interrupt Service Routine associated with the interrupt with higher priority will start. In order to avoid possible conflicts between the interrupt masking set in the main program, or inside high level language compiler macros, the GIP is put in AND through the User Global Interrupt Mask or the Macro Global Interrupt Mask (see Figure 5.2). The UEGI/UDGI instruction switches the User Global Interrupt Mask enabling/disabling the GIR for the main program. MEGI/MDGI instructions switch the Macro Global Interrupt Mask on/off in order to ensure that the macro will not be interrupted. Figure 5.2 Global Interrupt Request Remark: A fuzzy routine can be interrupted only in the Main program. When a Fuzzy function is running inside another interrupt routine an interrupt request can cause side effects in the Control Unit. For this reason, in order to use a Fuzzy function inside an interrupt routine, the user MUST include the Fuzzy function between an UDGI (MDGI) instruction and an UEGI (MEGI) instruction (see the following paragraphs), in order to disable the interrupt request during the execution of the fuzzy function. Global Interrupt Pending User Global Interrupt Mask Macro Global Global Interrupt Request 38/106 ST52F501L/F502L 5.3 Interrupt Sources ST FIVE manages interrupt signals generated by the internal peripherals or generated by software by the TRAP instruction or coming from the Port pins. There are two kinds of interrupts coming from the Port pins: the NMI and the Ports Interrupts. NMI (Not Maskable Interrupt) is associated with pin PA7 when it is configured as Alternate Function. This interrupt source doesn't have a configurable level priority and cannot be masked. The fixed priority level is lower than the software TRAP and higher than all the other interrupts. The NMI can be configured to be active on the rising or the falling edge. The Port Interrupts sources are connected with Port A, Port B and Port C pins. The pins belonging to the same Port are associated with the same interrupt vector: one vector for Port A and one shared by Port B and C. In order to use one port pin as interrupt, it must be configured as an interrupt source (see I/O Ports chapter). In this manner, up to 24 Port Interrupt sources are available. By reading the Port the sources that belong to the same Port can be discriminated. The Port Interrupts can be configured to be active on the rising or the falling edge. 5.4 Interrupt Maskability and Priority Levels Interrupts can be masked by the corresponding INT_MASK Configuration Register 0 (00h). An interrupt is enabled when the mask bit is "1". Vice versa, when the bit is "0", the interrupt is masked and the eventual requests are kept pending. All the interrupts, with the exception of the NMI and TRAP that have fixed level priority, have a configurable priority level. The configuration of the priority levels is completed by writing three consecutive Configuration Registers: INT_PRIORITY_H, INT_PRIORITY_M, INT_PRIORITY_L, addresses from 2 to 4 (02h-04h). The 24 bits of these registers are divided into 8 groups of three bits: each group is associated with a priority level. The three bits of each group are written with the code number associated with the interrupt source. See Table 5.1 to know the codes. Warning: changing the NMI or Port Interrupt polarity an interrupt request is generated. All the interrupt sources are filtered, in order to avoid false interrupt requests caused by glitches. The Trap instruction is something between a interrupt and a call: it generated an interrupt request at top priority level and the control is passed to the associated interrupt routine which vector is located in the fixed addresses 30-32. This routine cannot be interrupted and it is serviced even if the interrupts are globally disabled. Remark: The priority levels Configuration Registers must be programmed with different values for each 3-bit groups to avoid erroneous operation. For this reason the Interrupt priority must be fixed at the beginning of the main program, because the reset values of the Configuration Registers correspond to an undefined configuration (all zeros). During program execution the interrupt priority can only be modified within the Main Program: it cannot be changed within an interrupt service routine. 5.5 Interrupt RESET When an interrupt is masked, all requests are not acknowledged and remain pending. When the pending interrupt is enabled it is immediately serviced. This event may be undesired; in order to avoid this a RINT instruction may be inserted followed by the code number that identifies the interrupt to reset the pending request. See Table 5.1 to know the codes. Note: Similarly to the CALL instruction, after a TRAP the flags are not stacked. Figure 5.3 Example of Interrupt Requests INT2 PRIORITY LEVEL 0 INT0 INT0 INT4 INT1 INT3 1 INT1 2 INT2 INT2 INT2 3 INT3 4 INT4 5 6 MAIN PROGRAM MAIN PROGRAM 39/106 ST52F501L/F502L 5.6 Register Description Interrupt Mask Register (INT_MASK) Configuration Register 0 (00h) Read/Write Reset Value: 0000 0000 (00h) 7 MSKPB MSKPA MSKI2C MSKLVD MSKSCI MSKT1 Interrupt Polarity Register (INT_POL) Configuration Register 1 (01h) Read/Write Reset Value: 0000 0000 (00h) 7 POLPB 0 POLPA POLNMI 0 MSKT0 MSKPHW Bit 7-3: Not Used Bit 2: POLPB Port B & C Interrupt Polarity 0: The Port B & C interrupt is triggered on the rising edge of the applied external signal. 1: The Port B & C interrupt is triggered on the falling edge of the applied external signal. Bit 1: POLPA Port A Interrupt Polarity 0: The Port A interrupt is triggered on the rising edge of the applied external signal. 1: The Port A interrupt is triggered on the falling edge of the applied external signal. Bit 0: POLNMI Non Maskable Interrupt Polarity 0: The NMI is triggered on the rising edge of the applied external signal. 1: The NMI is triggered on the falling edge of the applied external signal. Bit 7: MSKPB Interrupt Mask Port B OR C 0: Port B OR C interrupt masked 1: Port B OR C interrupt enabled Bit 6: MSKPA Interrupt Mask Port A 0: Port A interrupt masked 1: Port A interrupt enabled Bit 5: MSKI2C Interrupt Mask I2C Interface 0: I2C Interface interrupt masked 1: I2C Interface interrupt enabled Bit 4: MSKLVD Interrupt Mask PLVD 0: PLVD interrupt masked 1: PLVD interrupt enabled Bit 3: MSKSCI Interrupt Mask SCI OR SPI 0: SCI OR SPI interrupt masked 1: SCI OR SPI interrupt enabled Bit 2: MSKT1 Interrupt Mask PWM/Timer 1 0: Pwm/Timer 1 interrupt masked 1: Pwm/Timer 1 interrupt enabled Bit 1: MSKT0 Interrupt Mask Pwm/Timer 0 0: Pwm/Timer 0 interrupt masked 1: Pwm/Timer 0 interrupt enabled Bit 0: MSKPHW Interrupt Mask PHW 0: PHW interrupt masked 1: PHW interrupt enabled High Priority Register (INT_PRL_H) Configuration Register 2 (02h) Read/Write Reset Value: 1111 1010 (FAh) 7 PRL23 PRL22 PRL21 PRL20 PRL19 PRL18 PRL17 0 PRL16 Medium Priority Register (INT_PRL_M) Configuration Register 3 (03h) Read/Write Reset Value: 1100 0110 (C6h) 7 PRL15 PRL14 PRL13 PRL12 PRL11 PRL10 PRL9 0 PRL8 40/106 ST52F501L/F502L Low Priority Register (INT_PRL_L) Configuration Register 4 (04h) Read/Write Reset Value: 1000 1000 (88h) 7 PRL7 PRL6 PRL5 PRL4 PRL3 PRL2 PRL1 0 PRL0 These three register are used to configure the priority level of each interrupt source. The 24 bits of these registers (PRL24-PRL0) are divided into 8 groups of three bits: each group is associated with a priority level (from level 1, the highest, to level 8, the lowest: level 0 is fixed for the NMI that can be interrupted only by the TRAP). The three bits of each group are written with the code number associated with the interrupt source (see Table 5.1). Table 5.1 Interrupt sources parameters Interrupt Source PHW PWM/Timer 0 PWM/Timer 1 IR Driver SCI / SPI (*) PLVD I2C Interface Port A Port B OR C NMI TRAP Priority type Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Fixed Fixed to highest PRL code 000 001 010 011 100 101 110 111 - PRL2-PRL1: Interrupt priority level 1 (highest) PRL5-PRL3: Interrupt priority level 2 PRL8-PRL6: Interrupt priority level 3 PRL11-PRL9:Interrupt priority level 4 PRL14-PRL12: Interrupt priority level 5 PRL17-PRL15: Interrupt priority level 6 PRL20-PRL18: Interrupt priority level 7 PRL23-PRL21: Interrupt priority level 8 (lowest) Example: writing the code 110 into PRL8-PRL6 bits the priority level 3 is assigned to the Port A Interrupt. Warning: the Priority Level configuration registers must be always configured. RINT code 0 1 2 3 4 5 6 7 8 - Maskable Yes Yes Yes Yes Yes Yes Yes Yes No No Vector Addresses 3-5 (03h-05h) 6-8 (06h-08h) 9-11 (09h-0Bh) 12-14 (0Ch-0Eh) 15-17 (0Fh-011h) 18-20 (012h-014h) 21-23 (015h-017h) 24-26 (018h-01Ah) 27-29 (01Bh-01Dh) 30-32 (01Eh-020h) (*) The interrupt 3 is shared between SCI and SPI. The two sources can be enabled selectively by their own interrupt enable bit in the Configuration Register. Further, they can be discriminated by reading their own status registers. 41/106 ST52F501L/F502L 6 CLOCK, RESET & POWER SAVING MODES 6.1 Clock The ST52F501L/F502L Clock Generator module generates the internal clock for the internal Control Unit, ALU and on-chip peripherals. The Clock is designed to require a minimum of external components. ST52F501L/F502L devices supply the internal oscillator in four clock modes: s External quartz oscillator s s s External clock External RC oscillator Internal oscillator The device always starts in internal clock mode, excluding any external clock source. After the start-up phase the clock is configured according to the user definition programmed in the Option Byte 0 (OSC_CR). The internal clock generator can supply an internal clock signal with a fixed frequency of 10 MHz 1%, without the need for external components. In order to obtain the maximum accuracy, the frequency can be calibrated by configuring the related Option byte 2 (OSC_SET). The internal clock can be divided by the configurable prescaler, set with the OSC_SET Option byte, by a factor 2, 4 or 8 thus obtaining 5 MHz, 2.5 MHZ and 1.25 MHZ clock frequency. The external oscillator mode uses a quartz crystal or a ceramic resonator connected to OSCin and OSCout as illustrated in Figure 6.1. This figure also illustrates the connection of an external clock. The ST52F501L/F502L oscillator circuit generates an internal clock signal with the same period and phase as the OSCIN input pin. The maximum frequency allowed is 24 MHz. When the external oscillator is used, the loop gain can be adapted to the various frequencies values by configuring the three bits of the Option Byte 1 CLK_SET (see Register Description, Table 6.2). Figure 6.1 Oscillator Connections CRYSTAL CLOCK When an external clock is used, it must be connected to the pin OSCIN while OSCOUT can be floating. In this case, Option Byte 1 bits must be written with 0 (000). The crystal oscillator start-up time is a function of many variables: crystal parameters (especially Rs), oscillator load capacitance (CL), IC parameters, environment temperature and supply voltage. The crystal or ceramic leads and circuit connections must be as short as possible. Typical values for CL1, CL2 are 10pF for a 20 MHz crystal. The clock signal can also be generated by an external RC circuit offering additional cost savings. Figure 6.1 illustrates the possible connections. Frequency is a function of resistor, capacitance, supply voltage and operating temperature; some indicative values when Vdd=1.8V and T=25, are shown in Table 6.1. The clock signal generates two internal clock signals: one for the CPU and one for the peripherals. The CPU clock frequency can be reduced, in order to decrease current conception, by setting the CPU_CLK Configuration Register 46 (02Eh). The CPU clock can be reduced up to 64 times (see Register Description). Table 6.1 RC Osc. indicative freq. (Vdd=1.8V) C (pF) R(K) 3.3 10 10 100 3.3 20 10 100 3.3 50 10 100 fosc (KHz) 6000 2500 300 4000 1500 187 2350 914 130 Variation 3% 3% 3% 3% 3% 5.5% 18% 18% 20% EXTERNAL CLOCK RC CIRCUIT CLOCK ST FIVE OSCin OSCout OSCin ST FIVE OSCout OSCin ST FIVE OSCout R Cl1 10pF Cl2 10pF CLOCK INPUT C Vdd Vss 42/106 ST52F501L/F502L 6.2 Reset Six reset sources are available: s RESET pin (external source) s s s s s The PDR works also in Wait and Halt modes, assuring a continuous monitoring of the device supply voltage. The PDR can be enabled/disabled with the Option Byte 3 (PLVD_SET) bit 7. 6.2.3 POR & Reset Procedures. After the Reset pin is set to Vdd or following a Power-On Reset event, a Power Down Reset or a Programmable Halt Wake-up reset (occurred in Halt mode), the device does not start until the internal supply voltage has reached the nominal level of around 1.75 V (typical: see electrical characteristics) when the PDR releases the reset. WATCHDOG (internal source) POWER ON Reset (Internal source) Low Voltage Detector (internal source) Power Down Reset (Internal source) Programmable Halt Wake-up (Internal source) When a Reset event occurs, the user program restarts from the beginning. 6.2.1 External Reset. Reset is an input pin. An internal reset does not affect this pin. A Reset signal originated by external sources is recognized immediately. The RESET pin may be used to ensure Vdd has risen to a point where the ICU can operate correctly before the user program is run. Reset must be set to Vdd in working mode. A Pull up resistor of 100 K guarantees that the RESET pin is at level "1" when no HALT or PowerOn events occur. If an external resistor is connected to the RESET pin a minimum value of 10K must be used. 6.2.2 Power Down Reset (PDR). In order to assure the device has correctly restarted, after the supply voltage has gone below the working level (around 1.75 V typical), the PDR supplies an internal reset of the device. The threshold is fixed in the range 1.7 V -1.85 V (typical: see electrical characteristics). An analog spike filtering of around 10 s is considered to avoid unwanted resets. Figure 6.2 Reset Block Diagram TCLK = Internal Clock period (100 ns) CKMOD1:0 = see Option Byte 0 (OSC_CR) W AKEUP = see Option Byte 7 (W AKEUP) PLVD WATCHDOG Warning: If the PDR is off, the POR cannot restart. To make the device restart correctly in this situation, the supply voltage VDD must drop to 0 V before restarting the device. After this level has been reached, the internal oscillator (10 MHz) is started and a delay period of 128 Internal clock cycles (12.8 s) is initiated, in order to allow the oscillator to stabilize and to ensure that recovery has taken place from the Reset state. Then, unless an external quartz clock is configured to be used, another short count of 4 Internal clock cycles (400 ns) starts before running the user program. Otherwise, if an external quartz clock has been configured to be used, the Option Byte 7 (WAKEUP) is read and counting starts before running the user program. The duration of the counting depends on the contents of the Option Byte 7 (WAKEUP), that works as a prescaler, according to the following formula: Delay = 128 x ( WAKEUP + 1 ) x Tclk WATCHDOG RESET PROGRAMMABLE LOW VOLTAGE DETECTOR RESET CKMOD1:0 INTERNAL / RC CLOCK 4 x TCLK INTERNAL RESET RESET 128 x TCLK QUARTZ CLOCK (W AKEUP+1) x 128 x TCLK Vdd POWER DOWN RESET POWER-ON RESET PDR PHW RESET (HALT MODE) PHW PHW RESET (RUN MODE) 43/106 ST52F501L/F502L This delay has been introduced in order to ensure that the oscillator has become stable after its restart, when a quartz clock is used. If the Reset is generated by the Programmable Low Voltage Detector or the Watchdog or the PHW (only in Run mode), the oscillator is not turned off; for this reason the CPU is then restarted immediately, without the delay. After a RESET procedure is completed, the core reads the instruction stored in the first 3 bytes of the Program/Data Memory, which contains a JUMP instruction to the first instruction of the user program. The Assembler tool automatically generates this Jump instruction with the first instruction address. 6.3 Programmable Low Voltage Detector The on-chip Programmable Low Voltage Detector (PLVD) circuit generates an interrupt request or a reset if the power supply drops below a configured level. The Reset/Interrupt option can be chosen by setting bit 2 of Option Byte 3 (PLVD_SET). If the interrupt option is chosen, the PLVD can be started choosing a threshold level by means of the Configuration Register 51 (033h) (PLVD_CR). Figure 6.3 Reset procedures flow Vdd = 0 In this case the PLVD can be enabled/disabled and the threshold changed in run time. When Vdd drops below the detection level, the related interrupt is served if enabled and the PLVD status bit 0 (PLVDST) in the PLVD_SR Input Register 57 (039h) is set to `1'. A new interrupt request cannot be generated until the Vdd rises up the trigger level. When the Vdd is above the trigger level the LVDST bit is `0'. If the Reset option has been set, the PLVD can be enabled and the threshold can be chosen only at start-up by means of the Option Byte 3 (PLVD_SET) bit 1:0. When the Vdd goes below the detection level, the device reset is generated; the reset is released only after the Vdd rises above the detection level. There are three levels with hysteresis for the PLVD falling voltages (see Electrical Characteristics). The PLVD circuit will only detect a drop if Vdd voltage stays below the safe threshold for at least 5s before activation/deactivation of the PLVD in order to filter voltage spikes. Remark: the PLVD function isn't active when it is in HALT mode. y POR_blk=ON ; POR=Vdd => RESET PDR=ON ; PDD=0 => RESET y Vdd > 1 y y Vdd = 0 Vdd > 1.45 y POR_blk=ON ; POR=0 => switches on EEPROM references and switches on the references for the PDR and PHW PDR=ON ; PDD=0 => RESET y y y Vdd < 1 Vdd > 1.75 y y Vdd > 1.75 PDR=ON ; PDD=0 => RESET => => POR_blk=ON ; POR=0 Legenda POR_blk = PowerOn block POR = PowerOn output signal PDR = PowerDown Reset block PDD = PowerDown output signal Rising Vdd slope Falling Vdd slope PDR=ON PDD=1=>POR_blk=OFF ; POR=0 y y Vdd > 1.75 44/106 ST52F501L/F502L 6.4 Power Saving modes There are two types of Power Saving modes: WAIT and HALT mode. These conditions may be entered by using the WAIT or HALT instructions. In Halt mode only the Programmable Halt mode Wake-up peripheral (PHW) can run, thus allowing the exiting from the Halt mode after a programmed time. 6.4.1 Wait Mode. Wait mode places the ICU in a low power consumption status by stopping the CPU. All peripherals and the watchdog remain active. During WAIT mode the Interrupts are enabled. The ICU remains in Wait mode until an Interrupt or a RESET occurs, whereupon the Program Counter jumps to the interrupt service routine or, if a Reset occurs, to the beginning of the user program. 6.4.2 Halt Mode. Halt mode is the lowest ICU power consumption mode, which is entered by executing the HALT instruction. The internal oscillator is turned off, causing all internal processing to be terminated, including the operations of the on-chip peripherals, with the exception of the PHW (see below) and PDR. Halt mode cannot be used when the watchdog is enabled. If the HALT instruction is executed while the watchdog system is enabled, it will be skipped without modifying the normal CPU operations. The ICU can exit Halt mode upon reception of an NMI, a Port Interrupt, a PHW interrupt (see below) or a Reset. The internal oscillator (10 MHZ) is started and a delay period of 128 clock cycles (12.8 s) is initiated, in order to allow the oscillator to stabilize and to ensure that recovery has taken place from the Reset state. Unless an external quartz clock is configured to be used, another short count of 4 Internal clock cycles (400 ns) starts before running the user program. Otherwise, if an external quartz clock has been configured to be used, the Option Byte 7 (WAKEUP) is read and another count is started before running the user program. The count duration depends on the contents of the Option Byte 7 (WAKEUP), that works as prescaler, according to the following formula: 6.5 Programmable Halt mode Wake-up (PHW) The PHW is a very low consumption Timer, designed to work even in Halt mode. Its working is based on a low power 32 kHz Internal Clock that drives a counter. The end of count can generate an interrupt or a reset and, if the device is in Halt mode, a wake-up from this state. The counter can execute a count from 26 to 216, corresponding to a time period from 2 ms to 2 s. Up to six configurable times are possible by setting Configuration Register 52 (034h) PHW_CR. It also allows the enabling/disabling or the selection of the interrupt/reset option (see Register Description). When the PHW_CR is latched, the counting is restarted with the new value. This peripheral has been designed to operate a wake-up from Halt mode at programmed time; nevertheless it can be used as a normal timer. Figure 6.4 WAIT Flow Chart WAIT ISTRUCTION OSCILLATOR PERIPHERALS CLOCK CPU CLOCK INTERRUPTS ON ON OFF ENAB. YES RESET NO CPU CLOCK ON NO INTERRUPT PROGRAM COUNTER RESET Delay = 128 x ( WAKEUP + 1 ) x Tclk This delay has been introduced in order to ensure that the oscillator has become stable after it is restarted. After the start up delay, by exiting with the NMI, a Port interrupt or PHW interrupt, the CPU restarts operations by serving the associated interrupt routine. CPU CLOCK ON JUMP TO INT. ROUTINE NORMAL PROGRAM FLOW 45/106 ST52F501L/F502L Figure 6.5 HALT Flow Chart HALT INSTRUCTION YES WATCHDOG ENABLED NO HALT INSTRUCTION SKIPPED OSCILLATOR PERIPHERALS CLOCK CPU CLOCK OFF OFF OFF NO NO RESET PHW / NMI / PORT INTERRUPT YES YES PHW or PORT INTERRUPT MASKED NO YES OSCILLATOR PERIPHERALS CLOCK CPU CLOCK ON ON ON OSCILLATOR PERIPHERALS CLOCK CPU CLOCK ON ON ON 128 INTERNAL CLOCK CYCLES DELAY 128 INTERNAL CLOCK CYCLES DELAY 4 INTERNAL CLOCK CYCLES DELAY NO EXT. QUARTZ CLOCK ? 4 INTERNAL CLOCK CYCLES DELAY NO EXT. QUARTZ CLOCK ? YES YES 128 X (WAKEUP+1) CLOCK CYCLES DELAY 128 X (WAKEUP+1) CLOCK CYCLES DELAY RESET CPU AND RESTART USER PROGRAM RESTART PROGRAM SERVICING THE INTERRUPT ROUTINE 46/106 ST52F501L/F502L 6.6 Register Description The following section describes the Register which are used to configure the Clock, Reset, PLVD and PHW. 6.6.1 Configuration Register. CPU Clock Prescaler (CPU_CLK) Configuration Register 46 (02Eh) Read/Write Reset Value: 0000 0000 (00h) 7 - Bit 7-2: Not Used Bit 1-0: PLVDI1-0 PLVD interrupt detection levels 00: PLVD disabled 01: Medium detection level 10: Lowest detection level 11: Highest detection level 0 CPUCK5 CPUCK4 CPUCK3 CPUCK2 CPUCK1 CPUCK0 Remark: The PLVDI1-0 bits are used only if the PLVD has been configured to generate a interrupt (PVDSEL=1 in PLVD_SET Option Byte), otherwise the PLVDR1-0 of the PLVD_SET Option Byte are used (see below) Bit 7-6: Not Used Bit 5-0: CPUCK5-0 CPU Clock Prescaler bits The CPU Clock frequency is divided by a factor described in the following table CPUCK5-0 000000 000001 000010 000100 001000 010000 100000 others CPU Clock fCPU=fOSC fCPU=fOSC/2 fCPU=fOSC/4 fCPU=fOSC/8 fCPU=fOSC/16 fCPU=fOSC/32 fCPU=fOSC/64 fCPU=fOSC/64 PHW Control Register (PHW_CR) Configuration Register 52 (034h) Read/Write Reset Value: 0000 0000 (00h) 7 5 0 PHWEN PHWSEL PHWC5 PHWC4 PHWC3 PHWC2 PHWC1 PHWC0 Bit 7: PHWEN Programmable Halt Wakeup Enable 0: PHW disabled 1: PHW enabled Bit 6: PHWSEL PHW Action selection 0: PHW generates a Interrupt 1: PHW generates a Reset Bit 5-0: PHWC5-0 PHW Counter 000000: Counter = 26 ~ 2 ms 000001: Counter = 26 ~ 2 ms 000010: Counter = 28 ~ 8 ms 000100: Counter = 210 ~ 32 ms 001000: Counter = 212 ~ 128 ms 010000: Counter = 214 ~ 512 ms 100000: Counter = 216 ~ 2 s PLVD Control Register (PLVD_CR) Configuration Register 51 (033h) Read/Write Reset Value: 0000 0000 (00h) 7 PLVDI1 0 PLVDI0 Note: if more than one bit is set in the PHW Counter, only the less significative will be considered. When a new value is latched, the count restarts. 47/106 ST52F501L/F502L 6.6.2 Option Bytes. Clock Mode (OSC_CR) Option Byte 0 (00h) Reset Value: 0000 0000 (00h) 7 OSPR1 Bit 7-3: Not Used Bit 2-0: CKPAR2-0 Oscillator Gains These three bits enable/disable the loop gains when a external clock or quartz are used for generating the clock. The following table describes the possible configuration options. Table 6.2 illustrates the recommended values for the most common frequencies used, time to start the oscillations and the settling time to have a duty cycle of 40%-60% (at steady state it is 50%). CKPAR2-0 000 001 010 011 100 101 Enabled Gain Stages No Gains (External Clock Mode) 1 gain stage enabled 2 gain stage enabled 3 gain stage enabled 4 gain stage enabled 5 gain stage enabled 6 gain stage enabled 7 gain stage enabled 0 OSPR0 CKMOD1 CKMOD0 Bit 7-4: Not used Bit 3-2: OSPR1-0 Internal Oscillator Prescaler 00: Internal Clock frequency = 10 MHz 01: Internal Clock frequency = 5 MHz 10: Internal Clock frequency = 2.5 MHz 11: Internal Clock frequency = 1.25 MHz Bit 1-0: CKMOD1-0 Clock Mode 00: Internal Oscillator 01: External Clock or quartz 1x: External RC oscillator External Clock Parameters (CLK_SET) Option Byte 1 (01h) Reset Value: 0000 0000 (00h) 7 - 110 111 0 CKPAR2 CKPAR1 CKPAR0 Warning: If an External Clock is used instead of a quartz or ceramic resonator, it is recommended that no gain be enabled (CKPAR2-0=000) in order to lower the current consumption. Table 6.2 Recommended Gains for the most common frequencies Frequency External Clock 1 MHz 5 MHz 10 MHz 16 MHz 20 MHz Recommend Gain Stages (1) 0 1 2 4 5 7 CKPAR2-0 000 001 010 100 101 111 Oscillation Start Times (2) 280 20.4 9.2 187 55 Settling Times for 60% duty-cycle (2) 150 60 11 50 18 (1) The recommended values have been chosen to have the best trade off between start time and current consumption. Higher gains give shorter Start times; lower gains give less current consumption. (2) Indicative values by design at 25 Celsius, VDD=1.8 V. Not Tested in production. 48/106 ST52F501L/F502L Internal Oscillator Calibration (OSC_SET) Option Byte 2 (02h) Reset Value: 0000 0000 (00h) 7 - 0 OSPAR5 OSPAR4 OSPAR3 OSPAR2 OSPAR1 OSPAR0 Remark: The PLVDR1-0 bits are used only if the PLVD has been configured to generate a reset (PVDSEL=0), otherwise the PLVDI1-0 of the PLVD_CR configuration register are used (see above) Bit 7-6: Not Used Bit 5-0: OSPAR5-0 Internal Oscillator Parameters These bits are used in order to calibrate the precision of the internal oscillator working at 10 MHz. The six bits enable some current generators with steps of 0.05 A corresponding to interval of frequency of 100KHz. Wake-Up Time Prescaler (WAKEUP) Option Byte 7 (07h) Reset Value: 0000 0000 (00h) 7 WK7 WK6 WK5 WK4 WK3 WK2 WK1 0 WK0 Warning: the maximum configuration value allowed for oscillator parameters OSPAR5:0 is 101000 (40). The value corresponding to the 10 MHz by design is 010100 (20). Bit 7-0: WK7-0 Wake-up prescaler This byte determinates the time delay for the stabilization of the oscillator after an External Reset or a POR and after the wake-up from Halt. The time delay is computed according to the following formula: PLVD & PDR Setup Register (PLVD_SET) Option Byte 3 (03h) Reset Value: 0000 0000 (00h) 7 PDREN - Delay = 128 x ( WAKEUP + 1 ) x Tclk Warning: If the internal clock is used as clock source the prescaler is not used. 0 PLVDSEL PLVDR1 PLVDR0 6.6.3 Input Registers. Bit 7: PDREN Power Down Reset Enable 0: PDR disabled 1: PDR enabled Bit 6-3: Not Used Bit 2: PLVDSEL PLVD Action selection 0: PLVD generates a Reset 1: PLVD generates a Interrupt Bit 1-0: PLVDR1-0 PLVD detection levels for reset 00: PLVD disabled 01: Lowest detection level 10: Medium detection level 11: Highest detection level IAP Status Register (IAP_SR) Input Register 40 (028h) Read only Reset Value: 0000 0000 (00h) 7 PLVDST PRTCD 0 ABRT Bit 7: PLVDST PLVD Status Register 0: Vdd below the current PLVD threshold 1: Vdd above the current PLVD threshold Bit 6-2: Not used Bit 1-0: See EEPROM Input Register paragraph 49/106 ST52F501L/F502L 7 FUZZY COMPUTATION (DP) The ST52F501L/F502L Decision Processor (DP) main features are: s Up to 8 Inputs with 8-bit resolution; s Figure 7.2 Alpha Weight Calculation j-th Mbf 1 1 Kbyte of Program/Data Memory available to store more than 300 to Membership Functions (Mbfs) for each Input; Up to 128 Outputs with 8-bit resolution; Possibility of processing fuzzy rules with an UNLIMITED number of antecedents; UNLIMITED number of Rules and Fuzzy Blocks. ij i-th INPUT VARIABLE s s s The limits on the number of Fuzzy Rules and Fuzzy program blocks are only related to the Program/Data Memory size. 7.1 Fuzzy Inference The block diagram shown in Figure 7.1 describes the different steps performed during a Fuzzy algorithm. The ST52F501L/F502L Core allows for the implementation of a Mamdami type fuzzy inference with crisp consequents. Inputs for fuzzy inference are stored in 8 dedicated Fuzzy input registers. The LDFR instruction is used to set the Input Fuzzy registers with values stored in the Register File. The result of a Fuzzy inference is stored directly in a location of the Register File. 7.2 Fuzzyfication Phase In this phase the intersection (alpha weight) between the input values and the related Mbfs (Figure 7.2) is performed. Eight Fuzzy Input registers are available for Fuzzy inferences. Figure 7.1 Fuzzy Inference After loading the input values by using the LDFR assembler instruction, the user can start the fuzzy inference by using the FUZZY assembler instruction. During fuzzyfication: input data is transformed in the activation level (alpha weight) of the Mbf's. 7.3 Inference Phase The Inference Phase manages the alpha weights obtained during the fuzzyfication phase to compute the truth value () for each rule. This is a calculation of the maximum (for the OR operator) and/or minimum (for the AND operator) performed on alpha values according to the logical connectives of Fuzzy Rules. Several conditions may be linked together by linguistic connectives AND/OR, NOT operators and brackets. The truth value and the related output singleton are used by the Defuzzyfication phase, in order to complete the inference calculation. 11 1 1m 2 FUZZYFICATION n1 nm INFERENCE PHASE N rules -1 N rules DEFUZZYFICATION Input Values Output Values 50/106 ST52F501L/F502L Figure 7.3 Fuzzyfication 7.5 Input Membership Function The Decision Processor allows the management of triangular Mbfs. In order to define an Mbf, three different parameters must be stored on the Program/Data Memory (see Figure 7.4): s the vertex of the Mbf: V; s IF INPUT 1 IS X1 OR INPUT 2 IS X2 THEN ....... 1 2 X1 Input 1 the length of the left semi-base: LVD; the length of the right semi-base: RVD; X2 Input 2 s OR = Max IF INPUT 1 IS X1 AND INPUT 2 IS X2 THEN ....... 1 2 X1 Input 1 In order to reduce the size of the memory area and the computational effort the vertical range of the vertex is fixed between 0 and 15 (4 bits) By using the previous memorization method different kinds of triangular Membership Functions may be stored. Figure 7.5 shows some examples of valid Mbfs that can be defined in ST52F501L/ F502L. Each Mbf is then defined storing 3 bytes in the first Kbyte of the Program/Data Memory. The Mbf is stored by using the following instruction: MBF n_mbf lvd v rvd X2 Input 2 7.4 Defuzzyfication In this phase the output crisp values are determined by implementing the consequent part of the rules. Each consequent Singleton Xi is multiplied by its weight values i, calculated by the Decision processor, in order to compute the upper part of the Defuzzyfication formula. Each output value is obtained from the consequent crisp values (Xi) by carrying out the following Defuzzyfication formula: N where: n_mbf is a tag number that identifies the Mbf lvd, v, and rvd are the parameters that describe the Mbf's shape as described above. Figure 7.4 Mbfs Parameters 15 Input Mbf Xij ij j Y i = --------------------N 0 V LVD Input Variable RVD ij j where: i = identifies the current output variable N = number of the active rules on the current output ij = weight of the j-th singleton Xij = abscissa of the j-th singleton The Decision Processor outputs are stored in the RAM location i-th specified in the assembler instruction OUT i. 15 w Output Singleton 0 X Output Variable 51/106 ST52F501L/F502L Figure 7.5 Example of valid Mbfs Figure 7.6 Output Membership Functions j-th Singleton 1 ij i0 in 0 X i0 X ij X in i-th OUTPUT 7.6 Output Singleton The Decision Processor uses a particular kind of membership function called Singleton for its output variables. A Singleton doesn't have a shape, like a traditional Mbf, and is characterized by a single point identified by the couple (X, w), where w is calculated by the Inference Unit as described earlier. Often, a Singleton is simply identified with its Crisp Value X. Table 7.1 Fuzzy Instructions Set Instruction MBF n_mbf Ivd v rvd IS n m ISNOT n m FZAND FZOR CON crisp OUT n_out FUZZY () 7.7 Fuzzy Rules Rules can have the following structures: if A op B op C...........then Z if (A op B) op (C op D op E...) ...........then Z where op is one of the possible linguistic operators (AND/OR) In the first case the rule operators are managed sequentially; in the second one, the priority of the operator is fixed by the brackets. Each rule is codified by using an instruction set, the inference time for a rule with 4 antecedents and 1 consequent is about 3 microseconds at 20 MHz. The Assembler Instruction Set used to manage the Fuzzy operations is reported in the table below. Description Stores the Mbf n_mbf with the shape identified by the parameters Ivd, v and rvd Fixes the alpha value of the input n with the Mbf m Calculates the complementary alpha value of the input n with the Mbf m. Implements the Fuzzy operation AND Implements the Fuzzy operation OR Multiplies the crisp value with the last weight Performs Defuzzyfication and stores the currently Fuzzy output in the register n_out Starts the computation of a single fuzzy variable Modify the priority in the rule evaluation 52/106 ST52F501L/F502L Example 1: IF Input1 IS NOT Mbf1 AND Input4 is Mbf12 OR Input3 IS Mbf8 THEN Crisp1 is codified by the following instructions: ISNOT 1 1 calculates the NOT value of Input1 with Mbf1 and stores the result in internal registers FZAND IS 4 12 FZOR IS 3 8 implements the operation AND between the previous and the next alpha value evaluated fixes the value of Input4 with Mbf12 and stores the result in internal registers implements the operation OR between the previous and the next alpha value evaluated fixes the value of Input3 with Mbf8 and stores the result in internal registers CON crisp1 multiplies the result of the last operation with the crisp value crisp1 Example 2, the priority of the operator is fixed by the brackets: IF (Input3 IS Mbf1 AND Input4 IS NOT Mbf15) OR (Input1 IS Mbf6 OR Input6 IS NOT Mbf14) THEN Crisp2 ( IS 3 1 FZAND parenthesis open to change the priority fixes the value of Input3 with Mbf1 and stores the result in internal registers implements the operation AND between the previous and the next alpha value evaluated ISNOT 4 15 calculates the NOT value of Input4 with Mbf15 and stores the result in internal registers ) FZOR ( IS 1 6 FZOR parenthesis closed implements the operation OR between the previous and the next alpha value evaluated parenthesis open to change the priority fixes the value of Input1 with Mbf6 and stores the result in internal registers implements the operation OR between the previous and the next alpha value evaluated ISNOT 2 14 calculates the NOT value of Input6 with Mbf14 and stores the result in internal registers ) CON crisp2 parenthesis closed multiplies the result of the last operation with the crisp value crisp2 At the end of the fuzzy rules related to the current Fuzzy Variable, by using the instruction OUT reg, the specified register is written with the computed value. Afterwards, the control of the algorithm returns to the CU. The next Fuzzy Variable evaluation must start again with a FUZZY instruction. 53/106 ST52F501L/F502L 8 I/O PORTS 8.1 Introduction ST52F501L/F502L are characterized by flexible individually programmable multi-functional I/O lines. The ST52F501L/F502L supplies devices with up to 3 Ports (named from A to C) with up to 24 I/O lines. Each pin can be used as a digital I/O or can be connected with a peripheral (Alternate Function). The I/O lines belonging to Port A and Port B can also be used to generate Port Interrupts. The I/O Port pins can be configured in the following modes: s Input high impedance (reset state) s s s s s s s 8.2 Input Mode The pins configured as input can be read by accessing the corresponding Port Input Register by means of the LDRI instruction. The addresses for Port A, B and C are respectively 0 (00h), 1 (01h), and 2 (02h). When executing the LDRI instruction all the signals connected to the input pins of the Port are read and the logical value is copied in the specified Register File location. If some pins are configured in output, the port buffer contents, which are the last written logical values in the output pins, are read. 8.3 Output Mode The pins configured as output can be written by accessing the corresponding Port Output Register by means of the LDPR, LDPI and LDPE instructions. The addresses for Port A, B and C are respectively, 0 (00h), 1 (01h), and 2 (02h). When executing the above mentioned instructions, the Port buffer is written and the Port pin signals are modified. If some pins are configured as input or as interrupt, the values are ignored. 8.4 Interrupt Mode The pins configured as Interrupt Mode can generate a Port Interrupt request. One Interrupt vector is associated to Port A and one to Port B and C. More pins of the ports can act as source at the same time. The Configuration Registers switch the signals deriving from interrupt pins to an OR gate that generates the interrupt request signal. The signal deriving from the pins can be read, allowing the discrimination of the interrupt sources when more than one pin can generate the interrupt signal. The interrupt trigger can be configured either in the rising or falling edge of the external signal. Input with pull-up Output with pull-up Output push-pull Output with weak pull-up Output open drain Interrupt with pull-up Interrupt without pull-up These eight modes can be selected by programming three Configuration Registers for each Port. All the pins that belong to the same Port can be configured separately by setting the corresponding bits in the three registers (see Register Description). To avoid side effects, the Configuration Registers register are latched only when the Direction Register (PORT_x_DDR) is written. For this reason this register must be always written when modifying the pin configuration. All the I/O digital pins are TTL compatible and have a Schmitt Trigger. The output buffer can supply high current sink (up to 8mA). Figure 8.1 Digital Pin P U LL U P ENA BLE DIG IT AL O UT ENA BLE D AT A OUT PAD PO R T A,C ,D,E P IN D AT A IN 54/106 ST52F501L/F502L 8.5 Alternate Functions The Alternate Function allows the pins to be connected with the peripheral signals or NMI. Not all Port pins have an Alternate Function associated. A Configuration Register (PORT_x_AF) for each Port is used to switch from the Digital I/O function or the Alternate Function. NMI is considered an Alternate Function. For this reason an NMI interrupt request can't be generated unless the PA7 pin is configured in Alternate Function and in one of the Input modes. When an on-chip peripheral is configured to use a pin, the correct I/O mode of the related pin should be selected by selecting one of the appropriate modes. See the Registers description in order to obtain the right configurations. Some peripherals, as for example the I2C peripheral, directly drive the pin configuration according to the current function, overriding the user configuration. 8.6 Register Description In order to configure the Port's pins, the three Configuration Registers PORT_x_PULLUP, PORT_x_OR and PORT_x_DDR must be configured. The combination of these three registers determine the pin's configuration, according to the scheme shown in Table 8.1. In order to select between the digital functions or Alternate functions PORT_x_AF register must be configured. Each bit of the configuration registers configures the pin of the corresponding position (example: PORT_A_DDR bit 5 configures the pin PA5). Figure 8.2 Port Pin Architecture CONF. REG. CONF. REG. CONF. REG. D E C O D E R EN SEL PU INT Vdd CONF. REG. ENABLE REGISTER FILE ALTERNATE FUNCTION DATA INTERRUPT POLARITY FF DIGITAL PORT PIN TO INPUT REGISTER IRQ 55/106 ST52F501L/F502L 8.6.1 Configuration Registers. Port A Pull-Up Register (PORT_A_PULLUP) Configuration Register 24 (018h) Read/Write Reset Value: 0000 0000 (00h) 7 PUA7 PUA6 PUA5 PUA4 PUA3 PUA2 PUA1 Bit 7: AFA7 Alternate Function PA7 0: Digital I/O 1: INT Bit 6: AFA6 Alternate Function PA6 0: Digital I/O 1: T0OUT Bit 5: AFA5 Alternate Function PA5 0: Digital I/O 1: TCLK, TX Bit 4: AFA4 Alternate Function PA4 0: Digital I/O 1: TSTRT Bit 3: AFA3 Alternate Function PA3 0: Digital I/O 1: RX Bit 2: AFA2 Alternate Function PA2 0: Digital I/O 1: T1OUT Bit 1: AFA1 Alternate Function PA1 0: Digital I/O 1: SDA Bit 0: AFA0 Alternate Function PA0 0: Digital I/O 1: SCL Table 8.1 Pin mode configuration 0 PUA0 Bit 7-0: PUA7-0 Port A pull-up (see Table 8.1) 0: Port A pin without pull-up 1: Port A pin with pull-up Port A Option Register (PORT_A_OR) Configuration Register 25 (019h) Read/Write Reset Value: 0000 0000 (00h) 7 ORA7 ORA6 ORA5 ORA4 ORA3 ORA2 ORA1 0 ORA0 Bit 7-0: ORA7-0 Port A option (see Table 8.1) Port A Data Direction Register (PORT_A_DDR) Configuration Register 26 (01Ah) Read/Write Reset Value: 0000 0000 (00h) 7 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 0 DDRA0 Bit 7-0: DDRA7-0 Port A direction (see Table 8.1) 0: Port A pin configured as input 1: Port A pin configured as output MODE Input high impedance Input with pull-up Interrupt without pull-up PU 0 1 0 1 0 1 0 1 OR 0 0 1 1 0 0 1 1 DDR 0 0 0 0 1 1 1 1 Port A Alternate Function (PORT_A_AF) Configuration Register 27 (01Bh) Read/Write Reset Value: 0000 0000 (00h) 7 AFA7 AFA6 AFA5 AFA4 AFA3 AFA2 AFA1 Interrupt with pull-up Output push-pull 0 Output with pull-up Output open drain Output weak pull-up AFA0 56/106 ST52F501L/F502L Port B Pull-Up Register (PORT_B_PULLUP) Configuration Register 28 (01Ch) Read/Write Reset Value: 0000 0000 (00h) 7 PUB7* PUB6* PUB5 PUB4 PUB3 PUB2 PUB1 Bit 7: AFB7 Alternate Function PB7 0: Digital I/O 1: T1OUT Bit 6: AFB6 Alternate Function PB6 0: Digital I/O 1: T0OUT Bit 5: AFB5 Alternate Function PB5 0: Digital I/O 1: TCLK Bit 4: AFB4 Alternate Function PB4 0: Digital I/O 1: TRES Bit 3: AFB3 Alternate Function PB3 0: Digital I/O 1: SS Bit 2: AFB2 Alternate Function PB2 0: Digital I/O 1: MISO Bit 1: AFB1 Alternate Function PB1 0: Digital I/O 1: MOSI Bit 0: AFB0 Alternate Function PB0 0: Digital I/O 1: SCK 0 PUB0 (*) Not used in 20 pin package devices Bit 7-0: PUB7-0 Port B pull-up (see Table 8.1) 0: Port B pin without pull-up 1: Port B pin with pull-up Port B Option Register (PORT_B_OR) Configuration Register 29 (01Dh) Read/Write Reset Value: 0000 0000 (00h) 7 ORB7* ORB6* ORB5 ORB4 ORB3 ORB2 ORB1 0 ORB0 (*) Not used in 20 pin package devices Bit 7-0: ORB7-0 Port B option (see Table 8.1) Port B Data Direction Register (PORT_B_DDR) Configuration Register 30 (01Eh) Read/Write Reset Value: 0000 0000 (00h) 7 DDRB7* DDRB6* DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 0 DDRB0 (*) Not used in 20 pin package devices Bit 7-0: DDRB7-0 Port B direction (see Table 8.1) 0: Port B pin configured as input 1: Port B pin configured as output Port C Pull-Up Register (PORT_C_PULLUP) Configuration Register 32 (020h) Read/Write Reset Value: 0000 0000 (00h) 7 PUC7* PUC6* PUC5 PUC4 PUC3 PUC2 PUC1 0 PUC0 Port B Alternate Function (PORT_B_AF) Configuration Register 31 (01Fh) Read/Write Reset Value: 0000 0000 (00h) 7 AFB7* AFB6* AFB5 AFB4 AFB3 AFB2 AFB1 (*) Not used in 28 pin package devices Note: This register is not used in 20 pin devices 0 AFB0 (*) Not used in 20 pin package devices Bit 7-0: PUC7-0 Port C pull-up (see Table 8.1) 0: Port C pin without pull-up 1: Port C pin with pull-up 57/106 ST52F501L/F502L Port C Option Register (PORT_C_OR) Configuration Register 33 (021h) Read/Write Reset Value: 0000 0000 (00h) 7 ORC7* ORC6* ORC5 ORC4 ORC3 ORC2 ORC1 0 ORC0 Bit 4: AFC4 Alternate Function PC4 0: Digital I/O 1: TX Bit 3: AFC3 Alternate Function PC3 0: Digital I/O 1: SS Bit 2: AFC2 Alternate Function PC2 0: Digital I/O 1: MISO Bit 1: AFC1 Alternate Function PC1 0: Digital I/O 1: MOSI Bit 0: AFC0 Alternate Function PC0 0: Digital I/O 1: SCK (*) Not used in 28 pin package devices Note: This register is not used in 20 pin devices Bit 7-0: ORC7-0 Port C option (see Table 8.1) Port C Data Direction Register (PORT_C_DDR) Configuration Register 34 (022h) Read/Write Reset Value: 0000 0000 (00h) 7 DDRC7* DDRC6* DDRC5 DDRC4 (*) Not used in 28 pin package devices DDRC3 DDRC2 DDRC1 0 DDRC0 Note: This register is not used in 20 pin devices Bit 7-0: DDRC7-0 Port C direction (see Table 8.1) 0: Port C pin configured as input 1: Port C pin configured as output Note: in order to achieve low current consumption, the port pins must be configured as input pull-up, even though they are not existing in the package. For example in 20 pin devices, the pins PB6-7 and PC0-7 must be configured in input pull-up. 8.6.2 Input Registers. Port C Alternate Function (PORT_C_AF) Configuration Register 35 (023h) Read/Write Reset Value: 0000 0000 (00h) 7 AFB5 AFB4 - Port A Data Input Register (PORT_A_IN) Input Register 0 (00h) Read only Reset Value: XXXX XXXX 0 PAI7 PAI6 PAI5 PAI4 PAI3 PAI2 PAI1 PAI0 7 0 Note: This register is not used in 20 pin devices Bit 7-6: Not Used Bit 5: AFC5 Alternate Function PC5 0: Digital I/O 1: TRES Bit 7-0: PAI7-0 Port A Input data The logical level applied in the Port A pins, configured as digital input, can be achieved by reading this register. 58/106 ST52F501L/F502L Port B Data Input Register (PORT_B_IN) Input Register 1 (01h) Read only Reset Value: XXXX XXXX 7 PBI7* PBI6* PBI5 PBI4 PBI3 PBI2 PBI1 Bit 7-0: PAO7-0 Port A Output data 0 PBI0 The logical values written in these register bits are put in the Port A pins configured as digital output. (*) Not used in 20 pin package devices Bit 7-0: PBI7-0 Port B Input data The logical level applied in the Port B pins, configured as digital input, can be achieved by reading this register. Port B Data Output Register (PORT_B_OUT) Output Register 1 (01h) Write only Reset Value: 0000 0000 (00h) 7 PBO7* PBO6* PBO5 PBO4 PBO3 PBO2 PBO1 0 PBO0 (*) Not used in 20 pin package devices Port C Data Input Register (PORT_C_IN) Input Register 2 (02h) Read only Reset Value: XXXX XXXX 7 PCI7* PCI6* PCI5 PCI4 PCI3 PCI2 PCI1 Bit 7-0: PBO7-0 Port B Input data The logical values written in these register bits are put in the Port B pins configured as digital output. 0 PCI0 (*) Not used in 28 pin package devices Port C Data Output Register (PORT_C_OUT) Output Register 2 (02h) Write only Reset Value: 0000 0000 (00h) 7 PCO7* PCO6* PCO5 PCO4 PCO3 PCO2 PCO1 Note: This register is not used in 20 pin devices Bit 7-0: PCI7-0 Port C Input data The logical level applied in the Port C pins, configured as digital input, can be achieved by reading this register. 8.6.3 Output Registers. Port A Data Output Register (PORT_A_OUT) Output Register 0 (00h) Write only Reset Value: 0000 0000 (00h) 7 PAO7 PAO6 PAO5 PAO4 PAO3 PAO2 PAO1 0 PCO0 (*) Not used in 28 pin package devices Note: This register is not used in 20 pin devices Bit 7-0: PCO7-0 Port C Input data The logical values written in these register bits are put in the Port C pins configured as digital output. 0 PAO0 59/106 ST52F501L/F502L 9 INSTRUCTION SET ST52F501L/F502L supplies 107 (98 + 9 Fuzzy) instructions that perform computations and control the device. Computational time required for each instruction consists of one clock pulse for each Cycle plus 2 clock pulses for the decoding phase. Total computation time for each instruction is reported in Table 9.1 The ALU of ST52F501L/F502L can perform multiplication (MULT) and division (DIV). Multiplication is performed by using 8 bit operands storing the result in 2 registers (16 bit values), see Figure 3.3. Division is performed between a 16 bit dividend and an 8 bit divider, the result and the remainder are stored in two 8-bit registers (see Figure 3.4). 9.1 Addressing Modes ST52F501L/F502L instructions allow the following addressing modes: s Inherent: this instruction type does not require an operand because the opcode specifies all the information necessary to carry out the instruction. Examples: NOP, SCF. s operands can refer (according to the opcode) to addresses belonging to the different addressing spaces. Example: SUB, LDRE. s Indirect: data addresses that are required are found in the locations specified as operands. Both source and/or destination operands can be addressed indirectly. The operands can refer, (according to the opcode) to addresses belonging to different addressing spaces. Examples: LDRR(reg1),(reg2); LDER mem_addr,(reg1). Bit Direct: operands of these instructions directly address the bits of the specified Register File locations. Examples: BSET, BTEST. s 9.2 Instruction Types ST52F501L/F502L supplies instruction types: s Load Instructions s s s s s the following Arithmetic and Logic Instructions Bitwise instructions Jump Instructions Interrupt Management Instructions Control Instructions Immediate: these instructions have an operand as a source immediate value. Examples: LDRC, ADDI. Direct: the operands of these instructions are specified with the direct addresses. The s The instructions are listed in Table 9.1 Table 9.1 Instruction Set Load Instructions Mnemonic BLKSET GETPG LDCE LDCI LDCNF LDCR LDER LDER LDER LDER LDFR Instruction BLKSET const GETPG regx LDCE confx,memy LDCI confx, const LDCNF regx, conf LDCR confx, regy LDER memx, regy LDER (regx),(regy) LDER (regx), regy LDER memx,(regy) LDFR fuzzyx, regy Bytes 2 2 3 3 3 3 3 3 3 3 3 Cycles (*) 7 8/9 7 7 8 10 11 10 11 8 Z S C - 60/106 ST52F501L/F502L Load Instructions (continued) LDPE LDPE LDPI LDPR LDRC LDRE LDRE LDRE LDRE LDRI LDRR LDRR LDRR LDRR PGSET PGSETR POP PUSH LDPE outx, memy LDPE outx, (regy) LDPI outx, const LDPR outx, regy LDRC regx, const LDRE regx, memy LDRE (regx), (regy) LDRE (regx), memy LDRE regx, (regy) LDRI regx, inpx LDRR regx, regy LDRR (regx), (regy) LDRR (regx), regy LDRR regx, (regy) PGSET const PGSETR regx POP regx PUSH regx 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 8/9 9/10 7 8 7 8/9 10/11 9/10 9/10 7 9 10 9 10 4 5 7 8 - Arithmetic Instructions Mnemonic ADD ADDC ADDI ADDIC ADDO ADDOC ADDOI ADDOIC AND ANDI CP CPI DEC Instruction ADD regx, regy ADDC regx, regy ADDI regx, const ADDIC regx, const ADDO regx, regy ADDOC regx, regy ADDOI regx, const ADDOICregx,cons AND regx, regy ANDI regx,const CP regx, regy CPI regx,const DEC regx Bytes 3 3 3 3 3 3 3 3 3 3 3 3 2 Cycles 9 9 8 8 11 11 10 10 9 8 8 7 7 Z I I I I I I I I I I I I I S I I I I I I I C I I I I I I I I - 61/106 ST52F501L/F502L Arithmetic Instructions (continued) DIV INC MIRROR MULT NOT OR ORI SUB SUBI SUBIS SUBO SUBOI SUBOIS SUBOS SUBS RCF RSF RZF SCF SSF SZF XOR XORI DIV regx, regy INC regx MIRROR regx MULT regx, regy NOT regx OR regx, regy ORI regx, const SUB regx, regy SUBI regx, const SUBIS regx, const SUBO regx, regy SUBOI regx, SUBOISregx,const SUBOS regx, regy SUBS regx, regy RCF RSF RZF SCF SSF SZF XOR regx, regy XORI regx, cons 3 2 2 3 2 3 3 3 3 3 3 3 3 3 3 1 1 1 1 1 1 3 3 16 7 7 11 7 9 8 9 8 8 11 10 10 11 9 4 4 4 4 4 4 9 8 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I - Bitwise Instructions Mnemonic ASL ASR BNOT BRES BSET BTEST MTEST RLC Instruction ASL regx ASR regx BNOT regx, bit BRES regx, bit BSET regx, bit BTEST regx, bit MTEST regx,const RLC regx Bytes 2 2 3 3 3 3 3 2 Cycles 7 7 8 8 8 7 7 7 Z I I I I I I I I S I C I I 62/106 ST52F501L/F502L Bitwise Instructions (continued) ROL ROR RRS ROL regx ROR regx RRS regx 2 2 2 7 7 7 I I I I I I - Jump Instructions Mnemonic CALL JP JPC JPNC JPNS JPNZ JPS JPZ RET Instruction CALL addr JP addr JPC addr JPNC addr JPNS addr JPNZ addr JPS addr JPZ addr RET Bytes 3 3 3 3 3 3 3 3 1 Cycles 11 6 5/6 5/6 5/6 5/6 5/6 5/6 8 Z S C - Interrupt Management Instructions Mnemonic HALT MEGI MDGI RETI RINT UDGI UEGI TRAP WAITI Instruction HALT MEGI MDGI RETI RINT INT UDGI UEGI TRAP WAITI Bytes 1 1 1 1 2 1 1 1 1 Cycles 4/13 6/11 5 9 6 5 6/11 9 7/10 Z S C - Control Instructions Mnemonic FUZZY NOP WDTRFR WDTSLP Instruction FUZZY NOP WDTRFR WDTSLP Bytes 1 1 1 1 Cycles 4 5 6 5 Z S C - 63/106 ST52F501L/F502L Notes: regx, regy: memx, memy: confx, confy: outx: inpx: const: fuzzyx: I - Register File Address Program/Data Memory Addresses Configuration Registers Addresses Output Registers Addresses Input Registers Addresses Constant value Fuzzy Input Registers flag affected flag not affected (*) The instruction BLKSET determines the start of a 32 byte block writing in Flash or EEPROM Program/ Data Memory. During this phase (about 4 ms), the CPU is stopped to executing program instructions. The duration of the BLKSET instruction can be identified with this time. 64/106 ST52F501L/F502L 10 WATCHDOG TIMER 10.1 Functional Description The Watchdog Timer (WDT) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The WDT circuit generates an ICU reset on expiry of a programmed time period, unless the program refreshes the WDT before the end of the programmed time delay. Sixteen different delays can be selected by using the WDT configuration register. After the end of the delay programmed by the configuration register, if the WDT is active, it starts a reset cycle pulling the reset signal low. Once the WDT is activated, the application program has to refresh the counter (by the WDTRFR instruction) during normal operation in order to prevent an ICU reset. In ST52F501L/F502L devices it is possible to choose between "Hardware" or "Software" Watchdog. The Hardware WDT allows the counting to avoid unwanted stops for external interferences. The first mode is always enabled unless the Option Byte 4 (WDT_EN) is written with a special code (10101010b): only this code can switch the WDT in "Software" Mode, the other 255 possibilities keep the "Hardware" Mode enabled. The WDT is started and refreshed by using the WDTRFR instruction. When the software mode is enabled, the WDTSLP instruction stops the WDT avoiding timeout resets. When the WDT is in Hardware Mode, neither the WDTSLP instruction nor external interference can stop the counting. The "Hardware" WDT is always enabled after a Reset. Figure 10.1 Watchdog Block Diagram Configuration Register D3 D2 D1 D0 The working frequency of WDT (PRES CLK in the Figure 10.1) is equal to the clock master. The clock master is divided by 500, obtaining the WDT CLK signal that is used to fix the timeout of the WDT. According to the WDT_CR Configuration Register values, a WDT delay between 0.1ms and 937.5ms can be defined when the clock master is 5 MHz. By changing the clock master frequency the timeout delay can be calculated according to the configuration register values. The first 4 bits of the WDT_CR register are used, obtaining 16 different delays. Table 10.1 Watchdog Timing Range (5 MHz) WDT timeout period (ms) min max 0.1 937.5 10.2 Register Description SW Watchdog Enable (WDT_EN) Option Byte 4 (04h) Reset Value: 0000 0000 (00h) 7 0 WDTEN7 WDTEN6 WDTEN5 WDTEN4 WDTEN3 WDTEN2 WDTEN1 WDTEN0 Bit 7-0: WDTEN7-0 SW Watchdog Enable byte Writing the code 10101010 in this byte the Software Watchdog mode is enabled. W DTRFR RESET PRES CLK = CLK MASTER WDT PRESCALER W TD CLK RESET GENERATOR RESET W DTSLP 65/106 ST52F501L/F502L Watchdog Control Register (WDT_CR) Configuration Register 7 (07h) Read/Write Reset Value: 0000 0001 (00h) 7 D3 D2 D1 0 D0 Bit 3-0: D3-0 Watchdog Clock divisor factor bits The Watchdog Clock (WDT CLK) is divided by the numeric factor determined by these bits, according with Table 10.2 and the following formula: 5 x 10 x DivisionFactor Timeout ( ms ) = ---------------------------------------------------------------Clock ( MHz ) 5 Bit 7-4: Not Used Table 10.2 Watchdog Timeout configuration examples WDT_CR(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Division Factor 5 MHz 1 625 1250 1875 2500 3125 3750 4375 5000 5625 6250 6875 7500 8125 8750 9375 0.1 62.5 125 187.5 250 312.5 375 437.5 500 562.5 625 687.5 750 812.5 875 937.5 Timeout Values (ms) 10 MHz 0.05 31.25 62.5 93.75 125 156.25 187.5 218.75 250 281.25 312.5 343.75 375 406.25 437.5 468.75 20MHz 0.025 15.625 31.25 46.875 62.5 78.125 93.75 109.375 125 140.625 156.25 171.875 187.5 203.125 218.75 234.375 66/106 ST52F501L/F502L 11 PWM/TIMERS AND IR DRIVER 11.1 Introduction ST52F501L/F502L offers two on-chip PWM/Timer peripherals. All ST52F501L/F502L PWM/Timers have the same internal structure. The timer consists of a 8-bit counter with a 16-bit programmable Prescaler, giving a maximum count of 224 (see Figure 11.1). Each timer has two different working modes, which can be selected by setting the correspondent bit TxMOD of the PWMx_CR1 Configuration Register: Timer Mode and PWM (Pulse Width Modulation) Mode. In addition the PWM/Timer 1 output can be used as input of the IR Driver (see below) to perform digital modulation of the digital carrier generated by the PWM/Timer 1 itself. All the Timers have Autoreload Functions; in PWM Mode the reload value can be set by the user. Each timer output is available on the apposite external pins configured in Alternate Function and in one of the Output modes. The outputs of both PWM/Timers can be synchronized and combined in OR, AND, XOR and NOT in order to generate complex wave modulation. PWM/Timer 0 can also use external START/STOP signals in order to perform Input capture and Output compare, external RESET signal, and external CLOCK to count external events: TSTRT, TRES and TCLK pins. In addition, the START/ STOP and RESET signals have configurable polarity (falling or rising edge). The Input Register PWMx_CAPTURE stores the counter value after the last Stop signal (only Timer Mode). The counter value is not stored after a Reset Signal. The peripheral status can also be read from the Input Registers (one for each Timer). These registers report START/STOP, SET/RESET status, TxOUT signal and the counter overflow flag. This last signal is set after the first EOC and it is reset by a Timer RESET (internal or external). 11.2 Timer Mode Timer Mode is selected writing 0 in the TxMOD bit. Each Timer requires three signals: Timer Clock (TMRCLKx), Timer Reset (TxRES) and Timer Start (TxSTRT) (see Figure 11.1). Each of these signals can be generated internally, and/or externally only for Timer 0, by using TRES, TSTRT and TCLK pins. The Prescaler output (PRESCOUT) increments the Counter value on the rising edge. PRESCOUT is obtained from the internal clock signal (CLKM) or, only for Timer 0, from the external signal provided on the apposite pin. Note: The external clock signal applied on the TCLK pin must have a frequency that is at least two times smaller than the internal master clock. The prescaler output period can be selected by setting the TxPRESC bits with one of the 17 division factors available. TMRCLK frequency is divided by a factor equal to the power of two of the prescaler values (up to 216). TxRES resets the content of the 8-bit counter to zero. It is generated by writing 0 in the TxRES bit of the PWMx_CR1 Configuration Register and/or it can be driven by the TRES pin if configured (only Timer0). Remark: To use TRES, TSTRT, TCLK external signals the related pins must be configured in Alternate Function and in one of Input modes. For each timer, the contents of the 8-bit counter are incremented on the Rising Edge of the 16-bit prescaler output (PRESCOUT) and it can be read at any instant of the counting phase by accessing the Input Register PWMx_COUNT_IN. Figure 11.1 PWM/Timer Counter block diagram 16-BIT PRESCALER CLKM BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 14 BIT 15 17 - 1 MULTIPLEXER PRESCx TMRCLK TxRES 8-BIT COUNTER BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 TxSTRT 67/106 ST52F501L/F502L Figure 11.2 Timer 0 External Start/Stop Mode start start stop start stop start Level E dge R eset C lock C ounted V alue 0 1 2 3 4 4 0 1 TxSTRT signal starts/stops the Timer from counting only if the peripherals are configured in Timer mode. The Timers are started by writing 1 in the TXSTRT bit of the PWMx_CR1 and are stopped by writing 0. This signal can be generated internally and/or externally by forcing the TSTRT pin (only TIMER0). TIMER 0 START/STOP can be given externally on the TSTRT pin. In this case, the T0STRT signal allows the user to work in two different configurable modes: s LEVEL (Time Counter): If the T0STRT signal is high, the Timer starts counting. When the T0STRT is low the timer stops counting and the 8-bit current value is stored in the PWM0_COUNT_IN Input Registers. s There can be two types of TxOUT waveforms: s type 1: TxOUT waveform equal to a square wave with a 50% duty-cycle s type 2: TxOUT waveform equal to a pulse signal with the pulse duration equal to the Prescaler output signal. EDGE (Period Counter): After reset, on the first T0STRT rising edge, TIMER 0 starts counting and at the next rising edge it stops. In this manner the period of an external signal may be measured. 11.3 PWM Mode The PWM working mode for each timer is obtained by setting the TxMOD bit of the Configuration Register PWMx_CR1. The TxOUT signal in PWM Mode consists of a signal with a fixed period, whose duty cycle can be modified by the user. The TxOUT period is fixed by setting the 16-bit Prescaler bits (TxPRESC) in the PWMx_CR2 and the 8-bit Reload value by writing the relative Output Register PWMx_RELOAD. The 16-bit Prescaler divides the master clock CLKM by powers of two, determining the maximum length period. Figure 11.3 TxOUT Signal Types The same above mentioned modes, can be used to reset the Timer0 by using the TRES pin signal. The polarity of the T0SRTR Start/Stop signal can be changed by setting the STRPOL and RESPOL bits in the INT_POL Configuration Register (01h bit 3 and 4). When these bits are set, the PWM/Timer 0 is Started/Set on the low level or in the falling edge of the signal applied in the pins. The Timer output signal, TxOUT, is a signal with a frequency equal to the one of the 16 bit-Prescaler output signal, PRESCOUTx, divided by a 8-bit counter set by writing the Output Register PWMx_COUNT_OUT. 68/106 Prescout*Counter Timer Output Type 1 Type 2 ST52F501L/F502L Figure 11.4 PWM Mode with Reload 255 compare value reload register 0 t PWM Output Ton T t Reload determines the maximum value that the counter can count before starting a new period. By setting the Reload value the counting resolution decreases. In order to obtain the maximum resolution, Reload value should be set to 0FFh and the period corresponds to the one established by the Prescaler value. The value set in the 8-bit counter by writing the Counter Output Register, determines the dutycycle: when count reaches the Counter value the TxOUT signal changes from high to low level. The period of the PWM signal is obtained by using the following formula: T=PWMx-RELOAD * 2TxPRESC * TMRCLKx where TxPRESC equals the value set in the TxPRESC bits of the PWMx_CR2 Configuration Register and TMRCLKx is the period of the Timer clock that drives the Prescaler. The duty cycle of the PWM signal is obtained by the following formula: By using a 24 MHz clock a PWM frequency that is close to 100 Khz can be obtained. The TIMER0 clock CLKM can also be supplied with an external signal, applied on the TCLK pin, which must have a frequency that is at least two times smaller than the internal master clock. Note: the Timers have to complete the previous counting phase before using a new value of the Counter. If the Counter value is changed during counting, the new values of the timer Counter are only used at the end of the previous counting phase. Nevertheless, it is recommended that the Reload value be written when the Timer is stopped in order to avoid incongruence with the Counter value. A Reload value greater than 1 must always be used. When the Timers are in Reset status, or when the device is reset, the TxOUT pins goes in threestate. If these outputs are used to drive external devices, it is recommended that the related pins be left in the default configuration (Input threestate) or change them in this configuration. In PWM mode the PWM/Timers can only be Set or Reset: Start/Stop signals do not affect the Timers. TxRES resets the content of the 8-bit counter to zero. It is generated by writing 0 in the corresponding TxRES bit of the PWMx_CR1 Configuration Register and/or it can be driven by the TRES pin if it is configured (only Timer0). T on PWMxCOUNT d cycle = ------- = ----------------------------------------T PWMxRELOAD Note: the PWM_x_COUNT value must be lower than or equal to the PWM_X_RELOAD value. When it is equal, the TxOUT signal is always at high level. If the Output Register PWM_x_COUNT is 0, TxOUT signal is always at a low level. 69/106 ST52F501L/F502L 11.3.1 Simultaneous Start. The PWM/Timers can be started simultaneously when working in PWM mode. The T0SYNC and T1SYNC bits in PWM0_CR3 Configuration Registers mask the reset of each timer; after enabling each single PWM/Timer. They are started by putting off the mask with a single writing in the PWM0_CR3 Register. Simultaneous start is also possible in Timer mode. The timers start counting simultaneously, but the output pulses are generated according to the modality configured (square or pulse mode). 11.4 Timer Interrupts The PWM/Timer can be programmed to generate an Interrupt Request, both on the falling and the rising of the TxOUT signal and when there's a STOP signal (external or internal). The PWM/ TIMER 1, when the IR Driver is active, can be configured to generate the IR interrupt (see below), excluding the other possible sources. By using the TxIES, TxIER and TxIEF bits of the Configuration Registers PWMx_CR1, the interrupt sources can be switched on/off. All the interrupt sources may be activated at the same time: sources can be distinguished by reading the PWMx_STATUS Input Register. The interrupt on the falling edge corresponds to half of a counting period in Timer mode when the waveform is set to Square Wave and to the end of the Ton phase in PWM mode. Note: when the PWM Counter is set to 0 or 65535, the interrupt occurs at the end of each control period. In order to be active, the PWM/Timers interrupts must be enabled by writing the Interrupt Mask Register (INT_MASK) in the Configuration Register Space, bits MSKT0 And MSKT1. Figure 11.5 PWM/Timers Output Modulation Architecture PWM/TIMER 0 T0OUT LOGIC UNIT FROM IR DRIVER FROM PWM/TIMER 0 PWM_LU_CR (0) 7 6 5 MUX_LU FROM PWM/TIMER 1 CONFIGURATION REGISTERS PWM_LU_CR (1) 4 3 2 1 0 T1OUT T1OUT PWM_LU_CR (5) PWM_LU_CR (4:0) IR DRIVER PWM/TIMER 1 70/106 ST52F501L/F502L 11.5 PWM/Timer output modulation The PWM/Timer outputs can be used to generate signal modulation for IR transmission in applications like Remote Control. This can be achieved by means of the Logic Unit or the IR Driver. Configuring register 50 (032h) PWM_LU_CR, T1OUTSEL bits, the T1OUT can output the signal coming from PWM/Timer 1, Logic Unit or the IR Driver (see Figure 11.5). 11.5.1 Logic Unit. The Logic Unit allows the combination of the T0OUT and T1OUT signals in order to generate digital signals, where one output is used as a carrier and the other as modulator. The resulting output goes to T1OUT pin. By setting the Configuration Register 50 (032h) PWM_LU_CR it is possible to combine the two outputs with the logic operators AND, OR NOT, XOR. The Logic Unit function should be used with the Simultaneous Start function to correctly synchronize the two signals. 11.5.2 IR Driver. The IR Driver implements the digital modulation of the digital carrier, T1OUT signal coming from the PWM/TIMER 1, and outputs it on the T1OUT pin. The resulting signal frequency is in the range 30 kHz - 80 kHz, according with the Clock frequency and the programmed Counter and Reload values. The IR Driver has been built to implement the most common protocols for Infrared Remote Control, such as: s Pulse Coded Signals s s s Shift Coded Signals RC5 The carrier is generated by the PWM/Timer 1, set in PWM mode, which generates a square wave with a period and duty cycle programmed by means of the PWM1_COUNT and PWM1_RELOAD 8-bit register, as explained in the previous paragraphs. When the start bit IRSTRT of the Configuration Register IR_CR1 is set to `1', the IR Driver generates a PWM signal with a period equal to IR_PERIOD (bits 6:0 of IR_CR1) times of the carrier period and duty cycle proportional to IR_DUTY (bits 6:0 of the IR_CR2 Configuration Register). The IRPOL bit (bit 7 of the IR_CR2 register) is used to define the polarity (i.e. the logical level) of the PWM signal at the start period: if IRPOL bit is `0" the PWM signal is al low level during the Ton and it is high during the Toff; vice versa if IRPOL is "1". The PWM signal obtained is used as a mask (logical AND) with the carrier signal, implementing the digital modulation. The figures below show some examples of modulation. By configuring the PWM_LU_CR Configuration Registers with the IR Driver output on T1OUT, the IR interrupt is automatically enabled. The interrupt is generated at the start of the "symbol" transmission, i.e. at the beginning of the period of the PWM modulator signal, to avoid dead times between two transmissions. Shape Coded Signals Note: When the IR Interrupt is enabled, the other PWM/Timer 1 interrupt sources are automatically disabled Figure 11.6 Pulse Coding signal modulation P1 D1 D0 P0 1 0 * Symbol "0" : * Symbol "1" : { { IR_PERIOD = P0 IR_DUTY IRPOL = D0 = `1' IR_PERIOD = P1 IR_DUTY IRPOL = D1 = `1' 71/106 ST52F501L/F502L Figure 11.7 Space Coding signal modulation P1 D D P0 1 0 * Symbol "0" : * Symbol "1" : { { IR_PERIOD = P0 IR_DUTY IRPOL =D = `1' IR_PERIOD = P1 IR_DUTY IRPOL =D = `1' Figure 11.8 Shift Coding signal modulation P1 D1 D0 P0 1 0 * Symbol "0" : * Symbol "1" : { { P IR_PERIOD = P0 IR_DUTY IRPOL = D0 = `1' IR_PERIOD = P1 IR_DUTY IRPOL = D1 = `1' Figure 11.9 RC5 Coding signal modulation P D D 1 0 * Symbol "0" : * Symbol "1" : { { IR_PERIOD = P IR_DUTY IRPOL =D = `0' IR_PERIOD = P IR_DUTY IRPOL =D = `1' 72/106 ST52F501L/F502L 11.6 PWM/Timer 0 Register Description The following registers are related to the use of the PWM/Timer 0. PWM/Timer 0 Control Register 2 (PWM0_CR2) Configuration Register 10 (0Ah) Read/Write Reset Value: 0000 0000 (00h) 7 4 T0WAV T0PRESC 0 PWM/Timer 0 Control Register 1 (PWM0_CR1) Configuration Register 9 (09h) Read/Write Reset Value: 0000 0000 (00h) 7 T0MOD T0IES T0IEF - 0 T0IER STRMOD T0STRT RESMOD T0RES Bit 7-6: Not Used Bit 5: T0WAV T0OUT Waveform 0: pulse (type2) 1: square (type1) Bit 4-0: T0PRESC PWM/Timer 0 Prescaler The PWM/Timer 0 clock is divided by a factor equal to 2T0PRESC. The maximum value allowed for T0PRESC is 10000 (010h). Bit 7: T0MOD PWM/Timer 0 Mode 0: Timer Mode 1: PWM Mode Bit 6: T0IES Interrupt on Stop signal Enable 0: interrupt disabled 1: interrupt enabled Bit 5: T0IEF Interrupt on T0OUT falling Enable 0: interrupt disabled 1: interrupt enabled Bit 4: T0IER Interrupt on T0OUT rising Enable 0: interrupt disabled 1: interrupt enabled Bit 3: STRMOD Start signal mode 0: start on level 1: start on edge Bit 2: T0STRT PWM/Timer 0 Start bit 0: Timer 0 stopped 1: Timer 0 started Bit 1: RESMOD Reset signal mode 0: reset on level 1: reset on edge Bit 0: T0RES PWM/Timer 0 Reset bit 0: PWM/Timer 0 reset 1: PWM/Timer 0 set PWM/Timer 0 Control Register 3 (PWM0_CR3) Configuration Register 11 (0Bh) Read/Write Reset Value: 0000 0000 (00h) 7 T1SYNC T0SYNC T0CKS STRSRC 0 RESSRC Bit 7: T0SYNC PWM/Timer 0 Set/Reset mask 0: Set/Reset activated 1: Set/Reset masked Bit 6: not used Bit 5: T1SYNC PWM/Timer 1 Set/Reset mask 0: Set/Reset activated 1: Set/Reset masked Bit 4: T0CKS PWM/Timer 0 Clock Source 0: Internal clock 1: External Clock from TCLK Bit 3-2: STRSRC PWM/Timer 0 Start signal source 00: Internal from T0STRT bit 01: External from TSTRT pin 10: Both internal and external 73/106 ST52F501L/F502L Bit 1-0: RESSRC PWM/Timer 0 Reset source 00: Internal from T0RES bit 01: External from TRES pin 10: Both internal and external PWM/Timer 0 Status Register (PWM0_STATUS) Input Register 23 (017h) Read only Reset Value: 0000 0000 (00h) 7 T0OVFL T0OUT T0RST 0 T0SST Interrupt Polarity Register (INT_POL) Configuration Register 1 (01h) Read/Write Reset Value: 0000 0000 (00h) 7 RESPOL STRPOL POLPB Bit 7-4: Not Used 0 POLPA POLNMI Bit 3: T0OVFL PWM/Timer 0 counter overflow flag 0: no overflow occurred since last reset 1: overflow occurred Bit 2: T0OUT T0OUT pin value 0: T0OUT pin is at logical level 0 1: T0OUT pin is at logical level 1 Bit 1: T0RST Reset Status 0: PWM/Timer 0 is reset 1: PWM/Timer 0 is set Bit 0: T0SST Start Status 0: PWM/Timer 0 is stopped 1: PWM/Timer 0 is running Bit 7-5: Not Used Bit 4: RESPOL Reset signal polarity 0: Reset on low level/rising edge 1: Reset on high level/falling edge Bit 3: STRPOL Start signal polarity 0: Start on high level/rising edge 1: Start on low level/falling edge Bit 2-0: See Interrupt Registers Description 11.6.1 PWM/Timer 0 Input Registers. PWM/Timer 0 Counter Input Register (PWM0_COUNT_IN) Input Register 22 (016h) Read only Reset Value: 0000 0000 (00h) 7 T0CI7 T0CI6 T0CI5 T0CI4 T0CI3 T0CI2 T0CI1 PWM/Timer 0 Capture Input Register (PWM0_CAPTURE) Input Register 25 (019h) Read only Reset Value: 0000 0000 (00h) 7 T0CP7 T0CP6 T0CP5 T0CP4 T0CP3 T0CP2 T0CP1 0 T0CP0 0 T0CI0 Bit 7-0: T0CP7-0 PWM/Timer 0 Capture LSB In this register the counter value after the last stop can be read. Bit 7-0: T0CI7-0 PWM/Timer 0 Counter In this register the current value of the Timer 0 Counter can be read. 74/106 ST52F501L/F502L 11.6.2 PWM/Timer 0 Output Registers. PWM/Timer 0 Counter Output Register (PWM0_COUNT_OUT) Output Register 8 (08h) Write only Reset Value: 0000 0000 (00h) 7 T0CO7 T0CO6 T0CO5 T0CO4 T0CO3 T0CO2 T0CO1 Bit 7: T1MOD PWM/Timer 1 Mode 0: Timer Mode 1: PWM Mode Bit 6: T1IES Interrupt on Stop signal Enable 0: interrupt disabled 1: interrupt enabled Bit 5: T1IEF Interrupt on T1OUT falling Enable 0: interrupt disabled 1: interrupt enabled Bit 4: T1IER Interrupt on T1OUT rising Enable 0: interrupt disabled 1: interrupt enabled Bit 3: not used Bit 2: T1STRT PWM/Timer 1 Start bit 0: Timer 0 stopped 1: Timer 0 started Bit 1: not used Bit 0: T1RES PWM/Timer 1 Reset bit 0: PWM/Timer 0 reset 1: PWM/Timer 0 set 0 T0CO0 Bit 7-0: T0CO7-0 PWM/Timer 0 Counter This register is used to write the Timer 0 Counter value. PWM/Timer 0 Reload Output Register (PWM0_RELOAD) Output Register 10 (0Ah) Write only Reset Value: 1111 1111 (0FFh) 7 0 T0REL7 T0REL6 T0REL5 T0REL4 T0REL3 T0REL2 T0REL1 T0REL0 Bit 7-0: T0REL7-0 PWM/Timer 0 Reload This register is used to write the Timer 0 Reload value. PWM/Timer 1 Control Register 2 (PWM1_CR2) Configuration Register 13 (0Dh) Read/Write Reset Value: 0000 0000 (00h) 11.7 PWM/Timer 1 Register Description The following registers are related to the use of the PWM/Timer 1, Logic Unit and IR Driver. 7 T1WAV 4 T1PRESC 0 11.7.1 PWM/Timer 1 Configuration Registers. PWM/Timer 1 Control Register 1 (PWM1_CR1) Configuration Register 12 (0Ch) Read/Write Reset Value: 0000 0000 (00h) 7 T1MOD T1IES T1IEF T1IER T1STRT - Bit 7-6: Not Used Bit 5: T1WAV T1OUT Waveform 0: pulse (type2) 1: square (type1) Bit 4-0: T1PRESC PWM/Timer 1 Prescaler The PWM/Timer 1 clock is divided by a factor equal to 2T1PRESC. The maximum value allowed for T1PRESC is 10000 (010h). 0 T1RES 75/106 ST52F501L/F502L IR Driver Control Register 1 (IR_CR1) Configuration Register 48 (030h) Read/Write Reset Value: 0000 0000 (00h) 7 IRSTRT IR_PERIOD Bit 6-0: IR_DUTY PWM modulator wave duty-cycle The duty-cycle of the modulator wave is equal to IR_DUTY/255. 0 Bit 7: IRSTRT IR Driver Start/Stop 0: IR Driver Stopped 1: IR Driver Started Bit 6-0: IR_PERIOD PWM modulator wave period The period of the modulator wave is equal to the carrier period multiplied the IR_PERIOD value. Logic Unit Control Register (PWM_LU_CR) Configuration Register 50 (032h) Read/Write Reset Value: 0000 0000 (00h) 7 LUNOT T1SEL 3 LUOP 0 Bit 7-6: Not Used Bit 5: LUNOT Logic Unit NOT operator 0: Logic Unit output not negated 1: Logic Unit output negated Bit 4: T1SEL T1OUT output signal selection 0: Logic Unit output 1: IR Driver output Bit 3-0: LUOP Logic Unit operator selection These bits configure the logic operation to be performed by the Logic Unit according to the following Table 11.1 IR Driver Control Register 2 (IR_CR2) Configuration Register 49 (031h) Read/Write Reset Value: 0000 0000 (00h) 7 IRPOL IR_DUTY 0 Bit 7: IRPOL Modulator wave Polarity 0: Modulator wave start with a low level 1: Modulator wave start with a high level Table 11.1 Logic Unit Operators Configuration Table PWM_LU_CR(5:0) bit 5 0 0 0 0 0 0 0 0 0 0 X X bit 4 0 0 0 0 0 0 0 0 0 1 1 1 bit 3 0 0 0 0 1 1 1 1 1 0 0 1 bit 2 0 0 1 1 0 0 0 0 1 0 1 0 bit 1 0 1 X X 0 0 1 1 X X X X bit 0 X X 0 1 0 1 0 1 X X X X T1 NOT(T1) T0 NOT(T0) NAND(T0,T1) = OR(NOT(T0),NOT(T1)) NAND(NOT(T0),T1) = OR(T0,NOT(T1)) NAND(T0,NOT(T1)) = OR(NOT(T0),T1) NAND(NOT(T0),NOT(T1)) = OR(T0,T1) XOR(T1,T2) IR DRIVER OUTPUT NULL NULL T1OUT 76/106 ST52F501L/F502L Table 11.1 Logic Unit Operators Configuration Table PWM_LU_CR(5:0) X 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 1 0 0 1 1 0 0 0 0 1 0 X 0 1 X X 0 0 1 1 X X X X X 0 1 0 1 0 1 X X T1OUT NULL NOT(T1) T1 NOT(T0) T0 AND(T0,T1) = NOR(NOT(T0),NOT(T1)) AND(NOT(T0),T1) = NOR(T0,NOT(T1)) AND(T0,NOT(T1)) = OR(NOT(T0),T1) AND(NOT(T0),NOT(T1)) = NOR(T0,T1) NOT(XOR(T0,T1)) NOT(IR DRIVER OUTPUT) Note: Tx = PWM/Timer x output signal X = don't care 11.7.2 PWM/Timer 1 Input Registers. PWM/Timer 1 Counter Input Register (PWM1_COUNT_IN) Input Register 27 (01Bh) Read only Reset Value: 0000 0000 (00h) 7 T1CI7 T1CI6 T1CI5 T1CI4 T1CI3 T1CI2 T1CI1 Bit 2: T1OUT T1OUT pin value 0: T1OUT pin is at logical level 0 1: T1OUT pin is at logical level 1 0 T1CI0 Bit 2: T1RST Reset Status 0: PWM/Timer 1 is reset 1: PWM/Timer 1 is set Bit 2: T1SST Start Status 0: PWM/Timer 1 is stopped 1: PWM/Timer 1 is running Bit 7-0: T1CI7-0 PWM/Timer 1 Counter In this register the current value of the Timer 1 Counter can be read. PWM/Timer 1 Status Register (PWM1_STATUS) Input Register 28 (01Ch) Read only Reset Value: 0000 0000 (00h) 7 T1OVFL T1OUT T1RST PWM/Timer 1 Capture Input Register (PWM1_CAPTURE) Input Register 30 (01Eh) Read only Reset Value: 0000 0000 (00h) 7 T1CP7 T1CP6 T1CP5 T1CP4 T1CP3 T1CP2 T1CP1 0 T1SST 0 T1CP0 Bit 7-4: Not Used Bit 7-0: T1CP7-0 PWM/Timer 1 Capture LSB Bit 3: T1OVFL PWM/Timer 1 counter overflow flag 0: no overflow occurred since last reset 1: overflow occurred In this register the counter value after the last stop can be read. 77/106 ST52F501L/F502L 11.7.3 PWM/Timer 1 Output Registers. PWM/Timer 1 Counter Output Register (PWM1_COUNT_OUT) Output Register 12 (0Ch) Write only Reset Value: 0000 0000 (00h) 7 T1CO7 T1CO6 T1CO5 T1CO4 T1CO3 T1CO2 T1CO1 PWM/Timer 1 Reload Output Register (PWM0_RELOAD) Output Register 14 (0Eh) Write only Reset Value: 1111 1111 (0FFh) 7 0 0 T1CO0 T1REL7 T1REL6 T1REL5 T1REL4 T1REL3 T1REL2 T1REL1 T01REL0 Bit 7-0: T1REL7-0 PWM/Timer 1 Reload This register is used to write the Timer 1 Reload value. Bit 7-0: T1CO7-0 PWM/Timer 0 Counter This register is used to write the Timer 1 Counter value. 78/106 ST52F501L/F502L 12 SERIAL COMMUNICATION INTERFACE The Serial Communication Interface (SCI) integrated into ST52F501L/F502L provides a general purpose shift register peripheral, several widely distributed devices to be linked, through their SCI subsystem. SCI gives a serial interface providing communication with the speed from less than 300 up to over 115200 baud, and a flexible character format. SCI is a full-duplex UART-type asynchronous system with standard Non Return to Zero (NRZ) format for the transmitted/received bit. The length of the transmitted word is 10/11 bits (1 start bit, 8/ 9 data bits, 1 stop bit). SCI is composed of three modules: Receiver, Transmitter and Baud-Rate Generator. 12.1 SCI Receiver block The SCI Receiver block manages the synchronization of the serial data stream and stores the data characters. The SCI Receiver is mainly composed of two sub-systems: Recovery Buffer Block and SCDR_RX Block. SCI receives data deriving from the RX pin and drives the Recovery Buffer Block, which is a highspeed shift register operating at a clock frequency (CLOCK_RX) 16 times higher than the fixed baud rate (CLOCK_TX). This sampling rate, higher than the Baud Rate clock, detects the START condition, Noise error and Frame error. When the SCI Receiver is in IDLE status, it is waiting for the START condition, which is obtained with a logic level of 0, consecutive to a logic level 1. This condition is detected if, with the fixed Figure 12.2 SCI Block Diagram SCI SCI Receiver Register File LDRI IR RECOVERY BUFFER SCDR_RX sampling time, a logic level 0 is sampled after three logic levels of 1. The recognition of the START bit forces the SCI Receiver Block to start a data acquisition sequence. The data acquisition sequence is configured by the apposite Configuration Register, allowing the following data frame formats (see Figure 12.1): Figure 12.1 SCI transmitted word structures STOP DATA START 10 9 8 7 6 5 4 3 2 1 0 STOP DATA START 9 8 7 6 5 4 3 2 1 0 s s s s 8 bit length, 1 stop bit, no parity bit 8 bit length, 2 stop bit, no parity bit 8 bit length, 1 stop bit, with parity bit 9 bit length, 1 stop bit, no parity bit The parity bit (if used) can be configured for even or odd parity check. If the 9-bit length format is configured, this bit is used in transmission for the ninth bit (see below). The ninth bit received can be read in the R8 bit of the SCI Status Register, address 37 (035h) bit 2 (see Figure 12.3). RX Program/Data Memory LDPR/LDPE/LDPI SCI Transmitter SHIFT REGISTER TX OR SCDR_TX MCLK Baud-Rate Generator 79/106 ST52F501L/F502L Recognition of a STOP condition transfers data received from the Recovery Buffer to the SCDR_RX buffer, adding the eventual ninth data bit. After this operation, RXF flag (bit 5) of SCI Status Input Register is set to logic level 1. The Control Unit reads data from the SCDR_RX buffer (in read-only mode) by reading the SCI_IN Input Register (address 36 024h) with the LDRI instruction and provides a reset at logic level 0 to the RXF flag. If data of the Recovery Buffer is ready to be transferred into the SCDR_RX buffer, but the previous one has not been read by the Core, an OVERRUN Error takes place: the SCI Status Register flag OVERR (bit 4) indicates the error condition. In this case, information that is stored in the SCDR_RX buffer is not altered, but the one that has caused the OVERRUN error can be overwritten by new data deriving from the serial data line. 12.1.1 Recovery Buffer Block . This block is structured as a synchronized finite state machine on the CLOCK_RX signal. When the Recovery Buffer Block is in IDLE state it waits for the reception of the correct 1 and 0 sequence representing START. Recognition takes place by sampling the input RX at CLOCK_RX frequency, which has a frequency that is 16 times higher than CLOCK_TX. For this reason, while the external transmitter sends a single bit, the Recovery Buffer Block samples 16 states (from SAMPLE1 to SAMPLE16). Analysis of the RX input signal is carried out by checking three samples for each bit received. If these three samples are not equal, then the noise error flag, NSERR (bit 7), of SCI Status Register is set to 1 and the data received value will be the one assumed by the majority of the samples. Figure 12.3 SCI Status Register The procedure described above, allows SCI not to becomes IDLE, because of a limited noise due to an erroneous sampling, the transmission is recognized as correct and the noise flag error is set. At the end of the cycle of the reception of a bit, the Recovery Buffer Block will repeat the same steps 9 times: one step for each bit received, plus one for the stop acquisition (10 times in case of 9-bit data, double stop or parity check). At the end of data reception the Recovery Buffer Block will supply information about eventual frame errors by setting the 1 FRERR flag (bit 6) of the SCI Status Register to 1. A frame error can occur if the parity check hasn't been successfully achieved or if the STOP bit has not been detected. If the Recovery Buffer Block receives 10 consecutive bits at logic level 0, a Line Break condition occurs, the related Interrupt Request is sent and the BRK flag in the SCI Status Register is set. 12.1.2 SCDR_RX Block. It is a finite state machine synchronized with the clock master signal, CKM. The SCDR_RX block waits for the signal of complete reception from the Recovery Buffer in order to load the word received. Moreover, the SCDR_RX block loads the values of FRERR and NSERR flag bits of the Status Register, and sets the RXF flag to 1. By using the LDRI instruction data is transferred to Register File and RXF flag is reset to 0, to indicate that the SCDR_RX block is empty. If new data arrives before the previous one has been transferred to Register File, the overrun error occurs and the OVERR flag of Status Register is set to 1. S C I_ S T A T U S In p u t R e g is te r 3 7 D7 D6 D5 D4 D3 D2 D1 D0 TXEND TXEM R8 BRK OVERR RXF FRERR NSERR - E N D T R A N S M IS S IO N - T R A N S M IS S IO N D A T A R E G IS T E R E M P T Y - R E C E IV E D N IN T H B IT - L IN E B R E A K - OVERRUN ERROR - R E C E IV E D A T A R E G IS T E R F U L L - FR AM E ER RO R - N O IS E E R R O R 80/106 ST52F501L/F502L 12.2 SCI Transmitter Block The SCI Transmitter Block consists of the following blocks: SCDR_TX and SHIFT REGISTER, synchronized, respectively, with the clock master signal (CKM) and the CLOCK_TX. The whole block receives the settings for the following transmission modes through the Configuration Register: s 8 bit length, 1 stop bit, no parity bit s s s 8 bit length, 2 stop bit, no parity bit 8 bit length, 1 stop bit, with parity bit 9 bit length, 1 stop bit, no parity bit In case of 9 bit frame transmission, the most significative bit arrives through the bit PAR/T8 (bit 2) of the SCI_CR1 Configuration Register. In an 8bit transmission, instead, this bit is used to configure the data format: in particular to choose the polarity control (even or odds) to implement the parity check (see above). After a RESET, the SCDR_TX block is in IDLE state until it receives an enabling signal by writing the TXSTRT bit of the SCI_CR2 Configuration Register. The data is loaded on the Peripheral Register SCI_OUT (address 23 017h) by using the instruction LPPR, LDPI or LDPE. If the transmission is enabled, the data to be transmitted is transferred from the Output Register to SCDR_TX block and the TXEM flag (bit 1) of the SCI Status Register is reset to 0 to indicate SCDR_TX block is full. If the core supplies new data, this could not be loaded in the SCDR_TX block until the current data has not been unloaded on the Shift Register block. Meaning that only when TXEM is 1 data can be loaded in the SCDR_TX Block. When the SHIFT REGISTER Block loads the data to be transmitted on an internal buffer, the TXEND flag (bit 0) of the SCI Status Register is reset to 0 to indicate the beginning of a new transmission. At the end of transmission TXEND is set to 1, allowing new data coming from SCDR_TX to be loaded in the SHIFT REGISTER. It is important to underline that TXEND = 1 does not mean SCDR_TX is ready to receive a new data. For this reason, it is better to utilize the TXEM signal to synchronize the load instruction to the SCI TRANSMITTER block If the TXSTRT bit is reset, the transmission is stopped, but the SCI Transmitter block completes the transmission in progress before resetting. 12.3 Baud Rate Generator Block The Baud Rate Generator Block performs the division of the clock master signal (CKM) in a set of synchronism frequencies for the serial bit reception/transmission on the external line. Reception frequency (CLOCK_RX) is 16 times higher than the transmission frequency (CLOCK_TX). To adapt the Baud Rate Generator to the clock master frequency supplied by the user, a 12-bit Prescaler must be programmed by loading the Configuration Registers SCI_CR2 (PRESC_H bit 11:8 of the 12 bit prescaler) and SCI_CR3 (PRESC_L bit 7:0 of the 12 bit prescaler). The prescaler allows the programming of all standard Baud Rates by using the most common clock master sources. The Prescaler value can be obtained by the following formula: CKM PRESC = round ---------------------------- 16 x BAUD Where CKM is the clock master frequency (expressed in Hz) and BAUD is the desired Baud Rate (expressed in bit/second). The obtained value is rounded to the nearest integer value. This rounding can cause an error in the obtained Baud Rate. This error must be lower than 3%. To verify that the PRESC value satisfies this constrain, the obtained Baud Rate must be computed by inverting the previous formula: CKM BAUD = -----------------------------16 x PRESC then the following relation can be used to verify that the difference with the desired Baud Rate is lower than 3%: BAUD - BAUD ------------------------------------------ < 0.03 BAUD Table 12.1 shows the recommended Prescaler values for common clock master frequencies. To get more precision in Baud Rate, standard quartz frequencies for serial communication can be used. The corresponding Prescaler values for these frequencies are showed in the Table 12.2. 81/106 ST52F501L/F502L Table 12.1 Recommended Prescaler values for common frequencies (Baud/MHz) 1 1200 2400 4800 9600 19200 38400 57600 115200 52 26 13 4 208 104 52 26 13 5 260 130 65 33 16 8 8 417 208 104 52 26 13 10 521 260 130 65 33 16 11 12 625 313 156 78 39 20 13 16 833 417 208 104 52 26 17 20 1042 521 260 130 65 33 22 11 24 1250 625 313 156 78 39 26 13 Table 12.2 Recommended Prescaler values for serial communication quartz (Baud/MHz) 1.843 1200 2400 4800 9600 19200 38400 57600 115200 96 48 24 12 6 3 2 1 2.458 128 64 32 16 8 4 3.686 192 96 48 24 12 6 4 2 4.915 256 128 64 32 16 8 6.144 320 160 80 40 20 10 7.373 384 192 96 48 24 12 8 4 9.830 512 256 128 64 32 16 11.059 576 288 144 72 36 18 12 6 12.288 640 320 160 80 40 20 13 14.746 768 384 192 96 48 384 16 8 19.661 1024 512 256 128 64 32 21 22.118 1152 576 288 144 72 36 24 12 82/106 ST52F501L/F502L 12.4 SCI Register Description The following registers are related to the use of the SCI peripheral. SCI Control Register 2 (SCI_CR2) Configuration Register 23 (017h) Read/Write Reset Value: 0000 0000 (00h) 7 4 PRESC_H - 2 0 RXSTRT TXSTRT 12.4.1 SCI Configuration Registers. SCI Control Register 1 (SCI_CR1) Configuration Register 22 (016h) Read/Write Reset Value: 0000 0000 (00h) 7 2 FRM 0 RXFINT OVRINT BRKINT TXEMINT TXENINT PAR/T8 Bit 7-4: PRESC_H Baud Rate prescaler (bit 11:8) These bits are the higher part of the prescaler (see SCI_CR3 Configuration Register) which determinates the baud rate of the communication, according to Table 12.1 and Table 12.2, as explained in Paragraph 12.3. Bit 3-2: not used Bit 1: RXSTRT Reception enable 0: RX disabled 1: RX enabled Bit 0: TXSTRT Transmission enable 0: TX disabled 1: TX enabled Bit 7: RXFINT SCDR_RX buffer full interrupt mask 0: interrupt disabled 1: interrupt enabled Bit 6: OVRINT Overrun interrupt mask 0: interrupt disabled 1: interrupt enabled Bit 5: BRKINT Break interrupt mask 0: interrupt disabled 1: interrupt enabled Bit 4: TXEMINT SCDR_TX buffer empty interrupt 0: interrupt disabled 1: interrupt enabled Bit 3: TXENINT TX end interrupt mask 0: interrupt disabled 1: interrupt enabled Bit 2: PAR/T8 Parity type selection or TX 9th bit 0: parity odd if enabled, else TX 9th bit=0 1: parity even if enabled, else TX 9th bit=1 Bit 1-0: FRM Frame type selection 00: 8 bit, no parity, 1 stop bit 01: 8 bit, no parity, 2 stop bit 10: 8 bit, parity, 1 stop bit 11: 9 bit, no parity, 1 stop bit SCI Control Register 3 (SCI_CR3) Configuration Register 43 (02Bh) Read/Write Reset Value: 0000 0000 (00h) 7 PRESC_L 0 Bit 7-0: PRESC_L Baud Rate prescaler (bit 7:0) These bits are the lower part of the prescaler (see SCI_CR2 Configuration Register) which determinates the baud rate of the communication, according to Table 12.1 and Table 12.2, as explained in Paragraph 12.3. Note: the SCI interrupts are not enabled unless the bit 3 (MSKSCI) of the Configuration Register 0 (INT_MASK) is enabled (set to 1). 83/106 ST52F501L/F502L 12.4.2 SCI Input Registers. SCI RX data Input Register (SCI_IN) Input Register 36 (024h) Read only Reset Value: 0000 0000 (00h) 7 RX7 RX6 RX5 RX4 RX3 RX2 RX1 Bit 4: OVERR Overrun error 0: overrun error not occurred 1: overrun error occurred Bit 3: BRK Line Break 0: Line Break not occurred 1: Line Break occurred Bit 2: R8 Received 9th bit 0: RX 9th bit=0 1: RX 9th bit=1 Bit 1: TXEM TX data register empty 0: TX data register full 1: TX data register empty Bit 0: TXEND TX end flag 0: data transferred to the shift register 1: data transmission completed 0 0 RX0 Bit 7-0: RX7-0 RX Data In this register the last received serial data can be read. SCI Status Register (SCI_STATUS) Input Register 37 (025h) Read only Reset Value: 0000 0011 (03h) 7 NSERR FRERR RXF OVERR BRK R8 TXEM TXEND 12.4.3 SCI Output Register. Bit 7: NSERR Noise error 0: noise error not occurred 1: noise error occurred Bit 6: FRERR Frame error 0: frame error not occurred 1: frame error occurred Bit 5: RXF RX data register full 0: RX data register already read 1: RX data register full but not read yet SCI TX data Output Register (SCI_OUT) Input Register 23 (017h) Write only Reset Value: 0000 0000 (00h) 7 TX7 TX6 TX5 TX4 TX3 TX2 TX1 0 TX0 Bit 7-0: TX7-0 TX Data In this register the serial data to be transmitted can be written. 84/106 ST52F501L/F502L 13 I2C BUS INTERFACE (I2C) 13.1 Introduction The I2C Bus Interface serves as an interface between the microcontroller and the serial I 2C bus, providing both multimaster and slave functions and controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I 2Bus Interface supports fast I2C mode (400kHz). 13.2 Main Features 2 s Parallel-bus/I C protocol converter s s s s s 13.3 General Description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. The interrupts are enabled or disabled via software. The interface is connected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). The interface can be connected both with a standard I2C bus and a Fast I2C bus. This selection is made via software. 13.3.1 Mode Selection. The interface can operate in the following four modes: - Slave transmitter/receiver - Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, providing Multi-Master capability. 13.3.2 Communication Flow. In Master mode, Communication Flow initiates data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software. In Slave mode the interface is capable of recognizing its own address (7 or 10-bit) and the General Call address. The General Call address detection may be enabled or disabled by software. Data and addresses are transferred as 8-bit bytes, (MSB first). The first byte(s) follow the start condition is the address (one in 7-bit mode, two in 10-bit mode), which is always transmitted in Master mode.A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Figure 13.1. Multi-master capability 7-bit/10-bit Addressing Transmitter/Receiver flag End-of-byte transmission flag Transfer problem detection I2C Master Features: s Clock generation s s s s s s I2C bus busy flag Arbitration Lost Flag End of byte transmission flag Transmitter/Receiver Flag Start bit detection flag Start and Stop generation I2C Slave Features: s Stop bit detection s s s s s s I2C bus busy flag Detection of misplaced start or stop condition Programmable I2C Address detection Transfer problem detection End-of-byte transmission flag Transmitter/Receiver flag Figure 13.1 I2C BUS Protocol SDA MSB SCL 1 START CONDITION 2 ACK 8 9 STOP CONDITION 85/106 ST52F501L/F502L Acknowledge may be enabled and disabled via software. The I2C interface address and/or general call address can be selected via software. The speed of the I2C interface may be selected between Standard (0-100KHz) and Fast I2C (100400KHz). 13.3.3 SDA/SCL Line Control. When the I2C cell is enabled, the SDA and SCL pins must be configured as floating open-drain I/O. The value of the external pull-up resistance used depends on the application. 13.4 Functional Description By default the I2C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. First, the interface frequency must be configured using the related bits of the Configuration Registers. 13.4.1 Slave Mode. As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface or the General Call address (if selected by software). Transmitter mode: the interface holds the clock line low before transmission, in order to wait for the microcontroller to write the byte in the Data Register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register. SCL frequency is controlled by a programmable clock divider which depends on the I2C bus mode. Figure 13.2 I2C Interface Block Diagram DATA REGISTER SDA SDA DATA CONTROL DATA SHIFT REGISTER COMPARATOR OWN ADDRESS REGISTER (OAR) SCL SCL CLOCK CONTROL CLOCK CONTROL REGISTER (I2C_CCR) CONTROL REGISTER (I2C_CR) STATUS REGISTER 1 (I2C_SR1) STATUS REGISTER 2 (I2C_SR2) CONTROL LOGIC INTERRUPT 86/106 ST52F501L/F502L Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address. Header matched (10-bit mode only): the interface generates an acknowledgement pulse if the ACK bit is set. Address not matched: the interface ignores it and waits for another Start condition. Address matched: the interface generates in sequence: - Acknowledge pulse if the ACK bit is set. - EVF and ADSL bits are set with an interrupt if the ITE bit is set. Afterwards, the interface waits for the I2C_SR1 register to be read, holding the SCL line low (see Figure 13.3 Transfer sequencing EV1). Next, in 7-bit mode read the I2C_IN register to determine from the least significant bit (Data Direction Bit) if the slave must enter Receiver or Transmitter mode. In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It will enter transmit mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1). Slave Receiver Following reception of the address and after the I2C_SR1 register has been read, the slave receives bytes from the SDA line into the I2C_IN register via the internal shift register. After each byte, the interface generates the following in sequence: - Acknowledge pulse if the ACK bit is set - EVF and BTF bits are set with an interrupt if the ITE bit is set. Afterwards, the interface waits for the I2C_SR1 register to be read followed by a read of the I2C_IN register, holding the SCL line low (see Figure 13.3 Transfer sequencing EV2). Slave Transmitter Following the address reception and after the I2C_SR1 register has been read, the slave sends bytes from the I2C_OUT register to the SDA line via the internal shift register. The slave waits for a read of the I2C_SR1 register followed by a write in the I2C_OUT register, holding the SCL line low (see Figure 13.3 Transfer sequencing EV3). When the acknowledge pulse is received: - The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Closing slave communication After the last data byte is transferred a Stop Condition is generated by the master. The interface detects this condition and sets: - EVF and STOPF bits with an interrupt if the ITE bit is set. Afterwards, the interface waits for a read of the I2C_SR2 register (see Figure 13.3 Transfer sequencing EV4). Error Cases - BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and the BERR bits are set with an interrupt if the ITE bit is set. If it is a Stop then the interface discards the data, released the lines and waits for another Start condition. If it is a Start then the interface discards the data and waits for the next slave address on the bus. - AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the ITE bit is set. Note: In both cases, the SCL line is not held low; however, SDA line can remain low due to possible 0 bits transmitted last. At this point, both lines must be released by software. How to release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the current byte is transferred. 13.4.2 Master Mode. To switch from default Slave mode to Master mode a Start condition generation is needed. Start condition Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition. Once the Start condition is sent: - The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set. Afterwards, the master waits for a read of the I2C_SR1 register followed by a write in the I2C_OUT register with the Slave address, holding the SCL line low (see Figure 13.3 Transfer sequencing EV5). 87/106 ST52F501L/F502L Slave address transmission At this point, the slave address is sent to the SDA line via the internal shift register. In 7-bit addressing mode, one address byte is sent. In 10-bit addressing mode, sending the first byte including the header sequence causes the following event: - The EVF bit is set by hardware with interrupt generation if the ITE bit is set. Afterwards, the master waits for a read of the I2C_SR1 register followed by a write in the I2C_OUT register, holding the SCL line low (see Figure 13.3 Transfer sequencing EV9). The second address byte is sent by the interface. After completion of this transfer (and acknowledge from the slave if the ACK bit is set): - The EVF bit is set by hardware with interrupt generation if the ITE bit is set. Afterwards, the master waits for a read of the I2C_SR1 register followed by a write in the I2C_CR register (for example set PE bit), holding the SCL line low (see Figure 13.3 Transfer sequencing EV6). Next, the master must enter Receiver or Transmitter mode. In order to close the communication: before reading the last byte from the I2C_IN register, set the STOP bit to generate the Stop condition. The interface automatically goes back to slave mode (M/SL bit cleared). Note: In order to generate the non-acknowledge pulse after the last data byte received, the ACK bit must be cleared just before reading the second last data byte. Master Transmitter Following the address transmission and after the I2C_SR1 register has been read, the master sends bytes from the I2C_OUT register to the SDA line via the internal shift register. The master waits for a read of the I2C_SR1 register followed by a write in the I2C_OUT register, holding the SCL line low (see Figure 13.3 Transfer sequencing EV8). When the acknowledge bit is received, the interface sets: - EVF and BTF bits with an interrupt if the ITE bit is set. In order to close the communication: after writing the last byte to the I2C_OUT register, set the STOP bit to generate the Stop condition. The interface automatically returns to slave mode (M/ SL bit cleared). Error Cases - BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and BERR bits are set by hardware with an interrupt if ITE is set. - AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the START or STOP bit. - ARLO: Detection of an arbitration lost condition. In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and the interface automatically goes back to slave mode (the M/SL bit is cleared). Note: In 10-bit addressing mode, in order to switch the master to Receiver mode, software must generate a repeated Start condition and resend the header sequence with the least significant bit set (11110xx1). Master Receiver Following the address transmission and after I2C_SR1 and I2C_CR registers have been accessed, the master receives bytes from the SDA line into the I2C_IN register via the internal shift register. After each byte the interface generates in sequence: - Acknowledge pulse if the ACK bit is set - EVFand BTF bits are set by hardware with an interrupt if the ITE bit is set. Afterwards, the interface waits for a read of the I2C_SR1 register followed by a read of the I2C_IN register, holding the SCL line low (see Figure 13.3 Transfer sequencing EV7). Note: In all these cases, the SCL line is not held low; however, the SDA line can remain low due to possible 0 bits transmitted last. Both lines must be released via software. 88/106 ST52F501L/F502L Figure 13.3 Transfer Sequencing 7-bit Slave receiver: S Address A EV1 Data1 A EV2 Data2 A EV2 ..... DataN A EV2 P EV4 7-bit Slave transmitter: S Address A EV1 EV3 Data1 A EV3 Data2 A EV3 ..... DataN NA EV3-1 P EV4 7-bit Master receiver: S EV5 Address A EV6 Data1 A EV7 Data2 A EV7 ..... DataN NA EV7 P 7-bit Master transmitter: S EV5 Address A EV6 EV8 Data1 A EV8 Data2 A EV8 ..... DataN A EV8 P 10-bit Slave receiver: S Header A Address A EV1 Data1 A EV2 ..... DataN A EV2 P EV4 10-bit Slave transmitter: Sr Header A EV1 EV3 Data1 A EV3 ..... DataN A EV3-1 P EV4 10-bit Master transmitter: S EV5 Header A EV9 Address A EV6 EV8 Data1 A EV8 ..... DataN A EV8 P 10-bit Master receiver: Sr EV5 Header A EV6 Data1 A EV7 ..... DataN A EV7 P Legend: S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge EVx=Event (with interrupt if ITE=1) EV1: EVF=1, ADSL=1, cleared by reading I2C_SR1 register. EV2: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by reading I2C_IN register. EV3: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register. EV3-1: EVF=1, AF=1, BTF=1, SCL=0; AF is cleared by reading I2C_SR2. BTF is cleared by releasing the lines (STOP=1,STOP=0) or by readyng I2C_SR1 and writing I2C_OUT register (I2C_OUT=FFh).Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen EV4: EVF=1, STOPF=1, cleared by reading I2C_SR2 register. EV5: EVF=1, SB=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register. EV6: EVF=1, cleared by reading I2C_SR1 register followed by writing I2C_CR (for example PE=1 EV7: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by reading I2C_IIN register. EV8: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register. EV9: EVF=1, ADD10=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT registe 89/106 ST52F501L/F502L Figure 13.4 Event Flags and Interrupt Generation ADD10 BTF ADSL SB AF STOPF ARLO BERR ITE INTERRUPT EVF * * EVF can also be set by EV6 or an error from the I2C_SR2 register. Interrupt Event Event Flag ADD10 BTF ADSEL SB Enable Control Bit Exit from Wait Yes Yes Yes Yes Exit from Halt No No No No No No No No 10-bit Address Sent Event (Master Mode) End of Byte Transfer Event Address Matched Event (Slave Mode) Start Bit Generation Event (Master Mode) Acknowledge Failure Event Stop Detection Event (Slave Mode) Arbitration Lost Event (Multimaster configuration) Bus Error Event ITE AF STOPF ARLO BERR Yes Yes Yes Yes Note: The I2C interrupt events are connected to the same interrupt vector. They generate an interrupt if the corresponding Enable Control Bit (ITE) is set and the Interrupt Mask bit (MSKI2C) in the INT_MASK Configuration Register is unmasked (set to 1, see Interrupts Chapter). 90/106 ST52F501L/F502L 13.5 Register Description In the following sections describe the registers used by the I2C Interface are described. 13.5.1 I2C Interface Configuration Registers. I2C Control Register (I2C_CR) Configuration Register 16 (010h) Read/Write Reset Value: 0000 0000 (00h) 7 PE ENGC START ACK STOP - In Slave Mode 0: No Start generation 1: Start generation when the bus is free Bit 2: ACK Acknowledge enable This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). 0: No acknowledge returned 1: Acknowledge returned after an address byte or a data byte is received Bit 1: STOP Reset signal mode This bit is set and cleared by software. It is also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE=0). - In Master Mode 0: No Stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent. - In Slave Mode 0: No actions performed 1: Release the SCL and SDA lines after the last byte transfer (BTF=1) in slave transmitter mode. In this mode the STOP bit has to be cleared by software. Bit 0: ITE Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled 0 ITE Bit 7-6: Not Used.They must be held to 0. Bit 5: PE Peripheral Enable. This bit is set and cleared by software 0: peripheral disabled 1: peripheral enabled Notes: - When PE=0, all the bits of the I2C_CR register and the SR register except the Stop bit are reset. All outputs are released while PE=0 - When PE=1, the corresponding I/O pins are selected by hardware as alternate functions. - To enable the I2C interface, write the I2C_CR register TWICE with PE=1 as the first write only activates the interface (only PE is set). Bit 4: ENGC Enable General Call This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). 0: General Call disabled 1: General Call enabled Note: The 00h General acknowledged (01h ignored). Call address is I2C Clock Control Register (I2C_CCR) Configuration Register 17 (011h) Read/Write Reset Value: 0000 0000 (00h) 7 FM/SM CC6 CC5 CC4 CC3 CC2 CC1 Bit 3: START Generation of a Start Condition This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent (with interrupt generation if ITE=1). - In Master Mode 0: No Start generation 1: Repeated Start generation 0 CC0 Bit 7: FM/SM Fast/Standard I2C Mode. This bit is set and cleared by software. It is not cleared when the interface is disabled (PE=0). 91/106 ST52F501L/F502L 1: Standard I2C Mode (recommended up to 100 kHz) 0: Fast I2C Mode (recommended up to 400 kHz) Bit 6-0: CC6-CC0 7-bit clock divider These bits select the speed of the bus (FSCL) depending on the I2C mode. They are not cleared when the interface is disabled (PE=0). The speed can be computed as follows: - Standard mode (FM/SM=1): F SCL <= 100kHz FSCL = fCPU/(3x[CC6..CC0]+11) - Fast mode (FM/SM=0): FSCL > 100kHz FSCL = fCPU/(2x[CC6..CC0]+9) I2C Own Address Register 2 (I2C_OAR2) Configuration Register 19 (013h) Read/Write Reset Value: 0000 0000 (00h) 7 - 2 ADD9 ADD8 0 - Bit 7-3: Not Used bit 7-1: ADD8-ADD8 Interface address. These are the most significant bits of the I2C bus address of the interface (10-bit mode only). They are not cleared when the interface is disabled (PE=0). Bit 0: Reserved Warning: For safety reason, CC6-CC0 bits must be configured with a value >= 3 for the Standard mode and >=2 for the Fast mode. 13.5.2 I2C Interface Input Registers. I2C Own Address Register 1 (I2C_OAR1) Configuration Register 18 (012h) Read/Write Reset Value: 0000 0000 (00h) 7 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 I2C Data Input Register (I2C_IN) Input Register 6 (06h) Read only Reset Value: 0000 0000 (00h) 0 7 I2CDI7 I2CDI6 I2CDI5 I2CDI4 I2CDI3 I2CDI2 I2CDI1 0 I2CDI0 ADD0 7-bit Addressing Mode bit 7-1: ADD7-ADD1 Interface address. These bits define the I2C bus address of the interface. They are not cleared when the interface is disabled (PE=0). Bit 0: ADD0 Address direction bit. This bit is "don't care", the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE=0). bit 7-0: I2CDI7-I2CDI0 Received data. These bits contain the byte to be received from the bus in Receiver mode: the first data byte is received automatically in the I2C_IN register using the least significant bit of the address. Then, the next data bytes are received one by one after reading the I2C_IN register. Note: Address 01h is always ignored. 10-bit Addressing Mode bit 7-0: ADD7-ADD0 Interface address. These are the least significant bits of the I2C bus address of the interface. They are not cleared when the interface is disabled (PE=0). I2C Status Register 1 (I2C_SR1) Input Register 7 (07h) Read only Reset Value: 0000 0000 (00h) 7 EVF ADD10 TRA BUSY BTF ADSL M/SL 0 SB 92/106 ST52F501L/F502L Bit 7: EVF Event Flag This bit is set by hardware as soon as an event occurs. It is cleared by software reading I2C_SR2 register in case of error event or as described in Figure 13.3. It is also cleared by hardware when the interface is disabled (PE=0). 0: No event 1: One of the following events has occurred: - BTF=1 (Byte received or transmitted) - ADSL=1 (Address matched in Slave mode while ACK=1) - SB=1 (Start condition generated in Master mode) - AF=1 (No acknowledge received after byte transmission) - STOPF=1 (Stop condition detected in Slave mode) - ARLO=1 (Arbitration lost in Master mode) - BERR=1 (Bus error, misplaced Start or Stop condition detected) - Address byte successfully transmitted in Master mode. Bit 6: ADD10 10 bit addressing in Master Mode This bit is set by hardware when the master has sent the first byte in 10-bit address mode. It is cleared by software reading I2C_SR2 register followed by a write in the I2C_OUT register of the second address byte. It is also cleared by hardware when the peripheral is disabled (PE=0). 0: No ADD10 event occurred 1: The Master has sent the first address byte Bit 5: TRA Transmitter/Receiver When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after detection of Stop condition (STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0). 0: Data byte received (if BTF=1) 1: Data byte transmitted Bit 4: BUSY Bus busy This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. This information is still updated when the interface is disabled (PE=0). 0: No communication on the bus 1: Communication ongoing on the bus Bit 3: BTF Byte transfer finished This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading I2C_SR1 register followed by a read of I2C_IN or write of I2C_OUT registers. It is also cleared by hardware when the interface is disabled (PE=0). - Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event (see Figure 13.3). BTF is cleared by reading I2C_SR1 register followed by writing the next byte in I2C_OUT register. - Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading I2C_SR1 register followed by reading the byte from I2C_IN register. The SCL line is held low while BTF=1. 0: Byte transfer not done 1: Byte transfer succeeded Bit 2: ADSL Address matched (Slave Mode) This bit is set by hardware as soon as the slave address received matched with the OAR register content or a general call is recognized. An interrupt is generated if ITE=1. It is cleared by software reading I2C_SR1 register or by hardware when the interface is disabled (PE=0). The SCL line is held low while ADSL=1. 0: Address mismatched or not received 1: Received address matched Bit 1: M/SL Master/Slave This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0). 0: Slave mode 1: Master mode Bit 0: SB Start bit (Master Mode) This bit is set by hardware as soon as the Start condition is generated (following a write 93/106 ST52F501L/F502L START=1). An interrupt is generated if ITE=1. It is cleared by software reading I2C_SR1 register followed by writing the address byte in I2C_OUT register. It is also cleared by hardware when the interface is disabled (PE=0). 0: No Start condition 1: Start condition generated After an ARLO event the interface switches back automatically to Slave mode (M/SL=0). The SCL line is not held low while ARLO=1. 0: No arbitration lost detected 1: Arbitration lost detected Bit 1: BERR Bus error. This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE=1. It is cleared by software reading I2C_SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while BERR=1. 0: No misplaced Start or Stop condition 1: Misplaced Start or Stop condition Bit 0: GCAL General Call (Slave mode). This bit is set by hardware when a general call address is detected on the bus while ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the interface is disabled (PE=0). 0: No general call address detected on bus 1: general call address detected on bus I2C Status Register 2 (I2C_SR2) Input Register 8 (08h) Read only Reset Value: 0000 0000 (00h) 7 AF STOPF ARLO BERR 0 GCAL Bit 7-5: Reserved. Bit 4: AF Acknowledge failure. This bit is set by hardware when an acknowledge is returned. An interrupt is generated if ITE=1. It is cleared by software reading the I2C_SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while AF=1. 0: No acknowledge failure 1: Acknowledge failure Bit 3: STOPF Stop detection (Slave mode). This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software reading I2C_SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while STOPF=1. 0: No Stop condition detected 1: Stop condition detected Bit 2: ARLO Arbitration lost. This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE=1. It is cleared by software reading I2C_SR2 register or by hardware when the interface is disabled (PE=0). 13.5.3 I2C Interface Output Registers. I2C Data Output Register (I2C_OUT) Output Register 6 (06h) Read only Reset Value: 0000 0000 (00h) 7 0 I2CDO7 I2CDO6 I2CDO5 I2CDO4 I2CDO3 I2CDO2 I2CDO1 I2CDO0 bit 7-0: I2CDO7-I2CDO0 Data to be transmitted. These bits contain the byte to be transmitted in the bus in Transmitter mode: Byte transmission start automatically when the software writes in the I2C_OUT register. 94/106 ST52F501L/F502L 14 SERIAL PERIPHERAL INTERFACE (SPI) 14.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master, one or more slaves, or a system, in which devices may be either masters or slaves. SPI is normally used for communication between the ICU and external peripherals or another ICU. Refer to the Pin Description section in this datasheet for the device-specific pin-out. 14.2 Main Features s Full duplex, three-wire synchronous transfers s s s s s s s s Master or slave operation Four master mode frequencies Maximum slave mode frequency = CKM/4. Four programmable master bit rates Programmable clock polarity and phase End of transfer interrupt flag Write collision flag protection Master mode fault protection capability. A basic example of interconnections between a single master and a single slave is illustrated in Figure 14.1 The MOSI pins are connected together as the MISO pins. In this manner, data is transferred serially between master and slave (most significant bit first). When the master device transmits data to a slave device via the MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). The transmitted byte is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. A status flag is used to indicate that the I/O operation is complete. Four possible data/clock timing relationships may be chosen (see Figure 14.4), but master and slave must be programmed with the same timing mode. 14.4 Functional Description Figure 14.2 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: - A Control Register (SPI_CR) - A Status Register (SPI_STATUS_CR) - A Data Register for transmission (SPI_OUT) - A Data Register for reception (SPI_OUT) 14.4.1 Master Configuration. In a master configuration, the serial clock is generated on the SCK pin. 14.3 General description SPI is connected to external devices through 4 alternate pins: - MISO: Master In / Slave Out pin - MOSI: Master Out / Slave In pin - SCK: Serial Clock pin - SS: Slave select pin (if not done through software) Figure 14.1 SPI Master Slave MASTER MSBit LSBit MISO SLAVE MSBit MISO LSBit 8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER MOSI MOSI SPI CLOCK GENERATOR SCK SS +5V SCK SS 95/106 ST52F501L/F502L Figure 14.2 Serial Peripheral Interface Block Diagram Internal Bus Read Read Buffer SPI_IN IT request MOSI MISO SPI_STATUS_CR 8-Bit Shift Register SPIF WCOL OR MODF SOD SSM SSI SPI_OUT Write SPI STATE CONTROL SCK SS SPI_CR SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 MASTER CONTROL SERIAL CLOCK GENERATOR Procedure - Select the SPR0, SPR1 and SPR2 bits to define the serial clock baud rate (see SPI_CR register). - Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 14.4). - The SS pin must be connected to a high level signal during the complete byte transmit sequence. - The MSTR and SPE bits must be set (they remain set only if the SS pin is connected to a high level signal). In this configuration the MOSI pin is a data output and to the MISO pin is a data input. Transmit sequence Transmit sequence begins when a byte is written in the SPI_OUT register. The data byte is loaded in parallel into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if the SPIE bit is set. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the SPI_IN register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPI_STATUS_CR register while the SPIF bit is set 2. A read to the SPI_IN register. Note: While the SPIF bit is set, all writes to the SPI_OUT register are inhibited until the SPI_STATUS_CR register is read. 96/106 ST52F501L/F502L 14.4.2 Slave Configuration. In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0, SPR1 and SPR2 bits is not used for data transfer. Procedure - For correct data transfer, the slave device must be in the same timing mode as the master device (CPOL and CPHA bits). See Figure 14.4. - The SS pin must be connected to a low level signal during the complete byte transmit sequence. - Clear the MSTR bit and set the SPE bit to assign the pins to alternate function. In this configuration the MOSI pin is a data input and the MISO pin is a data output. Transmit Sequence The data byte is loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if SPIE bit is set. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the SPI_IN register is read, the SPI peripheral returns the buffer value. The SPIF bit is cleared by the following software sequence: 1. An access to the SPI_STATUS_CR register while the SPIF bit is set. 2. A read to the SPI_IN register. (shifted in serially). The serial clock is used to synchronize data transfer during a sequence of eight clock pulses. The SS pin allows individual selection of a slave device; the other slave devices that are not selected do not interfere with SPI transfer. Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits. The CPOL (clock polarity) bit controls the steady state value of the clock when data isn't being transferred. This bit affects both master and slave modes. The combination between the CPOL and CPHA (clock phase) bits select the data capture clock edge. Figure 14.4, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. The SS pin is the slave device select input and can be driven by the master device. The master device applies data to its MOSI pinclock edge before the capture clock edge. CPHA bit is set The second edge on the SCK pin (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data is latched on the occurrence of the second clock transition. A write collision should not occur even if the SS pin stays low during a transfer of several bytes (see Figure 14.3). CPHA bit is reset The first edge on the SCK pin (falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the MSBit capture strobe. Data is latched on the occurrence of the first clock transition. The SS pin must be toggled high and low between each byte transmitted (see Figure 14.3). In order to protect the transmission from a write collision a low value on the SS pin of a slave device freezes the data in its SPI_OUT register and does not allow it to be altered. Therefore, the SS pin must be high to write a new data byte in the SPI_OUT without producing a write collision. 14.4.4 Write Collision Error. A write collision occurs when the software tries to write to the SPI_OUT register while a data transfer 97/106 Note: While the SPIF bit is set, all writes to the SPI_OUT register are inhibited until the SPI_STATUS_CR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 14.4.6). Depending on the CPHA bit, the SS pin has to be set to write to the SPI_OUT register between each data byte transfer to avoid a write collision (see Section 14.4.4). 14.4.3 Data Transfer Format. During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received ST52F501L/F502L is taking place with an external device. When this occurs, the transfer continues uninterrupted; and the software writing will be unsuccessful. Write collisions can occur both in master and slave mode. WCOL bit The WCOL bit in the SPI_STATUS_CR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). The WCOL bit is cleared by a software sequence (see Section 14.5). 14.4.5 Master Mode Fault. Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: - The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. - The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. - The MSTR bit is reset, forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read or write access to the SPI_STATUS_CR register while the MODF bit is set. 2. A write to the SPI_CR register. Note: a "read collision" will never occur since the data byte received is placed in a buffer, in which access is always synchronous with the ICU operation. In Slave mode When the CPHA bit is set: The slave device will receive a clock (SCK) edge prior to the latch of the first data transfer. This first clock edge will freeze the data in the slave device SPI_OUT register and output the MSBit on to the external MISO pin of the slave device. The SS pin low state enables the slave device, but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge occurs. When the CPHA bit is reset: Data is latched on the occurrence of the first clock transition. The slave device doesn't have a way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the SPI_OUT register after its SS pin has been pulled low. For this reason, the SS pin must be high, between each data byte transfer, in order to allow the CPU to write in the SPI_OUT register without generating a write collision. In Master mode Collision in the master device is defined as a write of the SPI_OUT register, while the internal serial clock (SCK) is in the process of transfer. The SS pin signal must always be high on the master device. Figure 14.3 CHPA/SS Timing Diagram Note: To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS pin must be pulled high during the clearing sequence of the MODF bit. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits, while the MODF bit is set (except in the MODF bit clearing sequence). In a slave device the MODF bit can't be set, but in a multi master configuration the device can be in slave mode with this MODF bit set. The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state using an interrupt routine. MOSI/MISO Master SS Slave SS (CPHA=0) Slave SS (CPHA=1) Byte 1 Byte 2 Byte 3 98/106 ST52F501L/F502L Figure 14.4 Data Clock Timing Diagram CPHA =1 CPOL = 1 CPOL = 0 MISO (from master) MOSI (from slave) SS (to slave) CAPTURE STROBE MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit CPHA =0 CPOL = 1 CPOL = 0 MISO (from master) MOSI (from slave) SS (to slave) CAPTURE STROBE MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter. 99/106 ST52F501L/F502L Figure 14.5 Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SPI_STATUS_CR OR THEN Read SPI_STATUS_CR THEN 2nd Step Read SPI_IN SPIF =0 WCOL=0 Write SPI_IN SPIF =0 WCOL=0 if no transfer has started WCOL=1 if a transfer has started before the 2nd step Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step Read SPI_STATUS_CR THEN 2nd Step Read SPI_IN WCOL=0 Note: Writing in SPI_OUT register instead of reading in SPI_IN do not reset WCOL bit 14.4.6 Overrun Condition. An overrun condition occurs when the master device has sent several data bytes and the slave device hasn't cleared the SPIF bit issued from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPI_IN register returns this byte. All other bytes are lost. This condition is not detected by the SPI peripheral. 14.4.7 Single Master and Multimaster Configurations. There are two types of SPI systems: - Single Master System - Multimaster System Single Master System A typical single master system may be configured, using an ICU as the master and four ICUs as slaves (see Figure 14.6). The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices. The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. Note: In order to prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission. For more security, the slave device may respond to the master with the data byte received. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written its SPI_OUT register. Other transmission security methods can use ports for handshake lines or data bytes with command fields. Multi-master System A multi-master system may also be configured by the user. Transfer of master control could be implemented using a handshake method through the I/O ports or by an exchange of code messages through the serial peripheral interface system. The multi-master system is principally handled by the MSTR bit in the SPI_CR register and the MODF bit in the SPI_STATUS_CR register. 100/106 ST52F501L/F502L Figure 14.6 Single Master Configuration SS SCK Slave MCU MOSI MISO SCK Slave MCU SS SCK Slave MCU SS SCK Slave MCU SS MOSI MISO MOSI MISO MOSI MISO MOSI MISO SCK Master MCU 3V SS Ports 14.4.8 Interrupts Enable Control Bit Exit from Wait Yes SPIE Master Mode Fault Event MODF Yes No Exit from Halt No Interrupt Event Event Flag SPIF SPI End of Transfer Event Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit (SPIE) and the interrupt mask bit (MSKSPI) in the INT_MASK Configuration Register is set. 101/106 ST52F501L/F502L 14.5 SPI Register Description In the following sections describe the registers used by the SPI. In the 16 pin devices the SPI is not present and the described register aren't used 14.5.1 SPI Configuration Registers. SPI Control Register (SPI_CR) Configuration Register 20 (014h) Read/Write Reset Value: 0000 0000 (00h) 7 SPIE SPE SPR2 MSTR CPOL CPHA SPR1 Bit 3: CPOL Clock polarity. This bit is set and cleared by software. This bit determines the steady state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin. 0 SPR2 Note: SPI must be disabled by resetting the SPE bit if CPOL is changed at the communication byte boundaries. Bit 2: CPHA Clock phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Bit 1-0: SPR1-SPR0 Serial peripheral rate. These bits are set and cleared by software. Used with the SPR2 bit, they select one of six baud rates to be used as the serial clock when the device is a master (see Table 14.1). These 2 bits have no effect in slave mode. Bit 7: SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF=1 or MODF=1 in SPI_STATUS_CR Bit 6: SPE Serial peripheral output enable. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 14.4.5 Master Mode Fault). 0: I/O port connected to pins 1: SPI alternate functions connected to pins Note: The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the pins. Bit 5: SPR2 Divider Enable. This bit is set and cleared by software and it is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 14.1. 0: Divider by 2 enabled 1: Divider by 2 disabled Remark: It is recommended to write the SPI_CR register after the SPI_STATUS_CR register when working in master mode, vice versa when working in slave mode. Table 14.1 Serial Peripheral Baud Rate Serial Clock fCKM/2 fCKM/4 fCKM/8 fCKM/16 fCKM/32 fCKM/64 SPR2 1 0 0 1 0 0 SPR1 0 0 0 1 1 1 SPR0 0 0 1 0 0 1 Note: This bit has no effect in slave mode. Bit 4: MSTR Master/Slave mode select. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 14.4.5 Master Mode Fault). 0: Slave mode is selected 1: Master mode is selected, the function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed. 102/106 SPI Control-Status Register (SPI_STATUS_CR) Configuration Register 21 (015h) Read/Write Reset Value: 0000 0000 (00h) 7 SPIF WCOL OR MODF SOD SSM 0 SSI ST52F501L/F502L Bit 7: SPIF Serial Peripheral data transfer flag. (read only) This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the SPI_CR register. It is cleared by a software sequence (an access to the SPI_STATUS_CR register followed by a read or write to the SPI_IN/ SPI_OUT registers). 0: Data transfer is in progress or has been approved by a clearing sequence. 1: Data transfer between the device and an external device has been completed. Bit 2: SOD SPI output disable This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output not disable 1: SPI output disable. Bit 1: SSM SS mode selection This bit is set and cleared by software. When set, it disables the alternate function of the SPI Slave Select pin and use the SSI bit value instead of. 0: SS pin used by the SPI. 1: SS pin not used (I/O mode), SSI bit value is used. Bit 0: SSI SS internal mode This bit is set and cleared by software. It replaces pin SS of the SPI when bit SSM is set to 1. SSI bit is active low slave select signal when SSM is set to 1. 0 : Slave selected 1 : Slave not selected. Note: While the SPIF bit is set, all writes to the SPI_OUT register are inhibited. Bit 6: WCOL Write Collision status (read only). This bit is set by hardware when a write to the SPI_OUT register is done during a transmit sequence. It is cleared by a software sequence (see Figure 14.5). 0: No write collision occurred 1: A write collision has been detected Bit 5: OR SPI overrun error (read only). This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPI_IN register while SPIF = 1 (See Section 14.4.6 Overrun Condition). It is cleared by a software sequence (read of the SPI_STATUS_CR register followed by a read in SPI_IN or write of the SPI_OUT register). 0: No overrun error. 1: Overrun error detected. Bit 4: MODF Mode Fault flag (read only). This bit is set by hardware when the SS pin is pulled low in master mode (see Section 14.4.5 Master Mode Fault). An SPI interrupt can be generated if SPIE=1 in the SPI_CR register. This bit is cleared by a software sequence (An access to the SPI_STATUS_CR register while MODF=1 followed by a write to the SPI_CR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bit 3: Not used. Remark: It is recommended to write the SPI_CR register after the SPI_STATUS_CR register when working in master mode, vice versa when working in slave mode. 14.5.2 SPI Input Register. SPI Data Input Register (SPI_IN) Input Register 5 (05h) Read only Reset Value: 0000 0000 (00h) 7 SPIDI7 SPIDI6 SPIDI5 SPIDI4 SPIDI3 SPIDI2 SPIDI1 0 SPIDI0 bit 7-0: SPIDI7-SPIDI0 Received data. The SPI_IN register is used to receive data on the serial bus. Note: During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. 103/106 ST52F501L/F502L Warning: A read to the SPI_IN register returns the value located in the buffer and not the contents of the shift register (see Figure 14.2). 14.5.3 SPI Output Register. SPI Data Output Register (SPI_OUT) Output Register 5 (05h) Write only Reset Value: 0000 0000 (00h) 7 0 SPIDO7 SPIDO6 SPIDO5 SPIDO4 SPIDO3 SPIDO2 SPIDO1 SPIDO0 bit 7-0: SPIDO7-SPIDO0 Data to be transmitted. The SPI_OUT register is used to transmit data on the serial bus. In the master device only a write to this register will initiate transmission/reception of another byte. Warning: A write to the SPI_OUT register places data directly into the shift register for transmission. 104/106 ST52F501L/F502L 105/106 Full Product Information at http://mcu.st.com Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Canada - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 106/106 |
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